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ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 1 ? copyright 2015?2016 xilinx, inc. xi linx, the xilinx logo, artix, ise, kintex, spartan, virtex, vivado, zynq, and other design ated brands included herein are trademarks of xilinx in the united states and other coun tries. amba, amba designer, arm, arm1176jz- s, coresight, cortex, and primecell are tr ademarks of arm in the eu and other countries. pci, pci express, pcie, and pci-x are trademarks of pci- sig. all other trademarks are the property of their respecti ve owners. summary the xilinx? kintex? ultrascale+? fpgas are available in -3, -2, -1 speed grades, with -3e devices having the highest performance. the -2le and -1li devices can operate at a v ccint voltage at 0.85v or 0.72v and provide lower maximum static po wer. when operated at a v ccint voltage at 0.72v, the -2le and -1li performance and static and dynamic power is reduced. however, when operated at a v ccint voltage of 0.85v using -2le and -1li devices, the speed specification for the l devices is the same as the -2i or -1i speed grades with reduced static power. dc and ac characteristics are specified in extended (e) and industrial (i) temp erature ranges. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (t hat is, the timing characteristics of a -1 speed grade extended device are the same as for a -1 speed grade industrial devi ce). however, only selected speed grades and/or devices are available in each temperature range. all supply voltage and junction temp erature specifications are representative of worst-case conditions. the parameters included are common to po pular designs and typical applications. this data sheet, part of an overall set of document ation on the kintex ultrascale+ fpgas, is available on the xilinx website at www.xilinx.com/documentation . dc characteristics kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 advance product specification table 1: absolute maximum ratings (1) symbol description min max units fpga logic v ccint internal supply voltage. ?0.500 1.000 v v ccint_io (2) internal supply voltage for the i/o banks. ?0.500 1.000 v v ccaux auxiliary supply vo ltage. ?0.500 2.000 v v ccbram supply voltage for the block ram memories. ?0.500 1.000 v v cco output drivers supply voltage for hd i/o banks. ?0.500 v output drivers supply voltage for hp i/o banks. ?0.500 v v ccaux_io (3) auxiliary supply voltage fo r the i/o banks. ?0.500 2.000 v v ref input reference voltage. v v in (4)(6)(7) i/o input voltage for hd i/o banks (5) .?0.500v i/o input voltage for hp i/o banks. ?0.550 v cco + 0.550 v v batt key memory battery backup supply ?0.500 2.000 v s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 2 i dc available output current at the pad. ma i rms available rms output current at the pad. ma gth or gty transceiver v mgtavcc analog supply voltage for the gth or gty transmitter and receiver circuits. ?0.500 1.000 v v mgtavtt analog supply voltage for the gth or gty transmitter and receiver termination circuits. ?0.500 1.300 v v mgtvccaux auxiliary analog quad pll (qpl l) voltage supply for the gth or gty transceivers. ?0.500 1.900 v v mgtrefclk gth or gty transceiver reference clock absolute input voltage. ?0.500 1.300 v v mgtavttrcal analog supply voltage for the resistor calibration circuit of the gth or gty transceiver column. ?0.500 1.300 v v in receiver (rxp/rxn) and transmitter (txp/txn) absolute input voltage. ?0.500 1.200 v i dcin-float dc input current for receiver input pins dc coupled rx termination = floating. ?ma i dcin-mgtavtt dc input current for receiver input pins dc coupled rx termination = v mgtavtt . ?0 (8) ma i dcin-gnd dc input current for receiver input pins dc coupled rx termination = gnd. ?0 (8) ma i dcin-prog dc input current for receiver input pins dc coupled rx termination = programmable. ?0 (8) ma i dcout-float dc output current for transmitter pins dc coupled rx termination = floating. ?ma i dcout-mgtavtt dc output current for transmitter pins dc coupled rx termination = v mgtavtt . ?ma system monitor v ccadc system monitor supply relative to gndadc. 0.500 2.000 v v refp system monitor reference input relative to gndadc. 0.500 2.000 v table 1: absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 3 temperature t stg storage temperature (ambient). ?65 150 c t sol maximum soldering temperature (9) .?260c t j maximum junction temperature (9) .?125c notes: 1. stresses beyond those listed under abso lute maximum ratings might cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. v ccint_io must be connected to v ccbram . 3. v ccaux_io must be connected to v ccaux . 4. the lower absolute voltage specification always applies. 5. if v cco is 3.3v, the maximum voltage is 3.4v. 6. for i/o operation, see the ultrascale architecture se lectio resources user guide ( ug571 ). 7. the maximum limit applied to dc signals. for maxi mum undershoot and overshoot ac specifications, see table 4 and table 5 . 8. for more information on supported gth or gty transceiver terminations see the ultrascale architecture gth transceiver user guide ( ug576 ) or ultrascale architecture gt y transceiver user guide ( ug578 ) 9. for soldering guidelines and thermal considerations, see the ultrascale and ultrascale+ fpgas packaging and pinout specifications ( ug575 ). table 1: absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 4 table 2: recommended oper ating conditions (1)(2) symbol description min typ max units fpga logic v ccint internal supply voltage. 0.825 0.850 0.876 v for -1li and -2le (0.72v only) devices: internal supply voltage. 0.698 0.720 0.742 v for -3e devices: internal supply voltage. 0.873 0.900 0.927 v v ccint_io (3) internal supply voltage for the i/o banks. 0.825 0.850 0.876 v for -1li and -2le devices (0.85v only): internal supply voltage for the i/o banks. 0.825 0.850 0.876 v for -3e devices: internal supply voltage for the i/o banks. 0.873 0.900 0.927 v v ccbram block ram supply voltage. 0.825 0.850 0.876 v for -3e devices: block ram supply voltage. 0.873 0.900 0.927 v v ccaux auxiliary supply voltage. 1.746 1.800 1.854 v v cco (4)(5) supply voltage for hd i/o banks. 1.140 ? 3.400 v supply voltage for hp i/o banks. 0.950 ? 1.900 v v ccaux_io (6) auxiliary i/o supply voltage. 1.746 1.800 1.854 v v in (7) i/o input voltage. ?0.200 ? v cco +0.200 v i in (8) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ?? ma v batt (9) battery voltage 1.000 ? 1.890 v gth or gty transceiver v mgtavcc (10) analog supply voltage for the gth or gty transceiver. 0.873 0.900 0.927 v v mgtavtt (10) analog supply voltage for the gth or gty transmitter and receiver termination circuits. 1.164 1.20 1.236 v v mgtvccaux (10) auxiliary analog qpll vo ltage supply for the transceivers. 1.746 1.80 1.854 v v mgtavttrcal (10) analog supply voltage for the resistor calibration circuit of the gth or gty transceiver column. 1.164 1.20 1.236 v s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 5 sysmon v ccadc sysmon supply relative to gndadc. 1.746 1.800 1.854 v v refp externally supplied reference voltage. 1.200 1.250 1.300 v temperature t j junction temperature operating range for extended (e) temperature devices. (11) 0? 100 c junction temperature operating range for industrial (i) temperature devices. ?40 ? 100 c notes: 1. all voltages are relative to gnd. 2. for the design of the power distribution system consult ultrascale architectu re pcb design guide ( ug583 ). 3. v ccint_io must be connected to v ccbram . 4. for v cco_0 , the minimum recomm ended operating voltage for power on and during configuration is 1.425v. after configuration, data is retained even if v cco drops to 0v. 5. includes v cco of 1.0v (hp i/o only), 1.2v, 1.35v, 1.5v, 1.8v, 2.5v (hd i/o only) at 5%, and 3.3v (hd i/o only) at +3/?5%. 6. v ccaux_io must be connected to v ccaux . 7. the lower absolute voltage specification always applies. 8. a total of 200 ma per 52-pin bank should not be exceeded. 9. if battery is not used, connect v batt to either gnd or v ccaux . 10. each voltage listed requires filtering as described in ultrascale architecture gt h transceiver user guide ( ug576 ) or ultrascale archit ecture gty transceiver user guide ( ug578 ). 11. devices labeled with the speed/temperature grade of -2le ca n operate for a limited time at a junction temperature of 110c. timing parameters adhere to the same speed file at 110c as they do below 110c, regardless of operating voltage (nominal voltage of 0.85v or a low- voltage of 0.72v). operation at t j = 110c is limited to 1% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does not exceed 1% of the device lifetime. table 2: recommended oper ating conditions (1)(2) (cont?d) symbol description min typ max units s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 6 table 3: dc characteristics over reco mmended operating conditions symbol description min typ (1) max units v drint data retention v ccint voltage (below which configuration data might be lost). ??v v draux data retention v ccaux voltage (below which configuration data might be lost). ??v i ref v ref leakage current per pin. ? ? a i l input or output leakage current per pin (sample-tested). (2) ?? a c in (3) die input capacitance at the pad (hp i/o). ? ? pf die input capacitance at the pad (hd i/o). ? ? pf i rpu pad pull-up (when selected) at v in =0v, v cco =3.3v. ? a pad pull-up (when selected) at v in =0v, v cco =2.5v. ? a pad pull-up (when selected) at v in =0v, v cco =1.8v. ? a pad pull-up (when selected) at v in =0v, v cco =1.5v. ? a pad pull-up (when selected) at v in =0v, v cco =1.2v. ? a i rpd pad pull-down (when selected) at v in =3.3v. ? a pad pull-down (when selected) at v in =1.8v. ? a i ccadcon analog supply current, analog circuits in power-up state. ? ? ma i ccadcoff analog supply current, analog circuits in power-down state. ? ? ma i batt (4)(5) battery supply current. 150 ? 250 na calibrated programmable on-die te rmination (dci) in hp i/o banks (7) (measured per jedec specification) r (8) thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_40. (6) 40 thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_48. (6) 48 thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_60. (6) 60 programmable input termination to v cco where odt = rtt_40. (6) 40 programmable input termination to v cco where odt = rtt_48. (6) 48 programmable input termination to v cco where odt = rtt_60. (6) 60 programmable input termination to v cco where odt = rtt_120. (6) 120 programmable input termination to v cco where odt = rtt_240. (6) 240 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 7 uncalibrated programmable on-die termination in hp i/o banks (measured per jedec specification) r (8) thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_40. 40 thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_48. 48 thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_60. 60 programmable input termination to v cco where odt = rtt_40. 40 programmable input termination to v cco where odt = rtt_48. 48 programmable input termination to v cco where odt = rtt_60. 60 programmable input termination to v cco where odt = rtt_120. 120 programmable input termination to v cco where odt = rtt_240. 240 uncalibrated programmable on-die termination in hd i/o banks (measured per jedec specification) r (8) thevenin equivalent resistance of programmable input termination to v cco /2 where odt = rtt_48. 48 internal v ref 50% v cco v cco x 0.49 v cco x 0.50 v cco x 0.51 v 70% v cco v cco x 0.69 v cco x 0.70 v cco x 0.71 v differential termination programmable differential termination (term_100) for hp i/o banks. ? 100 ? n temperature diode ideality factor. ? 1.026 ? ? r temperature diode series resistance. ? ? notes: 1. typical values are specified at nominal voltage, 25c. 2. for hp i/o banks with a v cco of 1.8v and separated v cco and v ccaux_io power supplies, the i l maximum current is 70 a. 3. this measurement represents the die capacitance at the pad, not including the package. 4. maximum value specified for worst case process at 25c. 5. i batt is measured when the battery-backed ram (bbram) is enabled. 6. if vrp resides at a different bank (dci cascade), the range increases to 15%. 7. vrp resistor tolerance is (240 1%) 8. on-die input termination resistance, for more information see the ultrascale architecture selectio resources user guide ( ug571 ). table 3: dc characteristics over reco mmended operating conditions (cont?d) symbol description min typ (1) max units s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 8 table 4: v in maximum allowed ac voltage overshoo t and undershoot for hd i/o banks (1) ac voltage overshoot % of ui at ?40c to 100c ac voltage undershoot % of ui at ?40c to 100c v cco +0.30 v cco +0.35 v cco +0.40 v cco +0.45 v cco +0.50 v cco +0.55 v cco +0.60 v cco +0.65 v cco +0.70 v cco +0.75 v cco +0.80 v cco +0.85 v cco +0.90 v cco +0.95 notes: 1. a total of 200 ma per bank should not be exceeded. table 5: v in maximum allowed ac voltage overshoo t and undershoot for hp i/o banks (1)(2) ac voltage overshoot % of ui at ?40c to 100c a c voltage undershoot % of ui at ?40c to 100c v cco +0.05 v cco +0.10 v cco +0.15 v cco +0.20 v cco +0.25 v cco +0.30 v cco +0.35 v cco +0.40 v cco +0.45 v cco +0.50 v cco +0.55 v cco +0.60 v cco +0.65 v cco +0.70 v cco +0.75 v cco +0.80 v cco +0.85 notes: 1. a total of 200 ma per bank should not be exceeded. 2. for ui smaller than 20 s. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 9 table 6: typical quiescent supply current (1)(2)(3) symbol description device speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 i ccintq quiescent v ccint supply current. xcku3p ma xcku5p ma xcku9p 1690 1607 1607 1409 1409 ma XCKU11P ma xcku13p ma xcku15p ma i ccint_ioq quiescent current for v ccint_io supply. xcku3p ma xcku5p ma xcku9p 61 59 59 59 59 ma XCKU11P ma xcku13p ma xcku15p ma i ccoq quiescent v cco supply current. xcku3p ma xcku5p ma xcku9p11111ma XCKU11P ma xcku13p ma xcku15p ma i ccauxq quiescent v ccaux supply current. xcku3p ma xcku5p ma xcku9p 273 273 273 273 273 ma XCKU11P ma xcku13p ma xcku15p ma i ccaux_ioq quiescent v ccaux_io supply current. xcku3p ma xcku5p ma xcku9p 33 33 33 33 33 ma XCKU11P ma xcku13p ma xcku15p ma s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 10 power-on/off power supply sequencing the recommended power-on sequence is v ccint , v ccint_io /v ccbram , v ccaux /v ccaux_io , and v cco to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the recommended power-off sequence is the reverse of the power-on sequence. if v ccint and v ccint_io /v ccbram have the same recommended voltage levels, th ey can be powered by the same supply and ramped simultaneously. v ccint_io must be connected to v ccbram . if v ccaux /v ccaux_io and v cco have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. v ccaux and v ccaux_io must be connected together. v ccadc and v ref can be powered at any time and have no power-up sequencing requirements. the recommended power-on sequence to achieve mini mum current draw for the gth or gty transceivers is v ccint , v mgtavcc , v mgtavtt or v mgtavcc , v ccint , v mgtavtt . there is no recommended sequencing for v mgtvccaux . both v mgtavcc and v ccint can be ramped simultaneous ly. the recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. if these recommended sequences are not met, current drawn from v mgtavtt can be higher than specifications during power-up and power-down. i ccbramq quiescent v ccbram supply current. xcku3p ma xcku5p ma xcku9p 48 45 45 45 45 ma XCKU11P ma xcku13p ma xcku15p ma notes: 1. typical values are specified at nomina l voltage, 85c junction temperatures (t j ) with single-ended selectio? resources. 2. typical values are for blank co nfigured devices with no output current loads, no active inpu t pull-up resistors, all i/o pins are 3-state and floating. 3. use the xilinx power estimator (xpe ) spreadsheet tool (download at www.xilinx.com/power ) to estimate static power consumption for conditions other than those specified. table 6: typical quiescent supply current (1)(2)(3) (cont?d) symbol description device speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 11 power supply requirements table 7 shows the minimum current, in addition to i ccq , that are required by the kintex ultrascale+ fpgas for proper power-on and configuration. if the current minimums shown in table 6 and table 7 are met, the device powers on after all supplies have passed th rough their power-on reset threshold voltages. the device must not be configured until after v ccint is applied. once initialized and configured, use the xilinx power estimator (xpe) tools to estimate current drain on these supplies. table 8 shows the power supply ramp time. table 7: power-on current by device device i ccintmin i ccint_iomin +i ccbrammin i ccomin i ccauxmin +i ccaux_iomin units xcku3p i ccintq + 770 i ccbramq +i ccint_ioq + 229 i ccoq +50 i ccauxq +i ccaux_ioq +386 ma xcku5p i ccintq + 770 i ccbramq +i ccint_ioq + 305 i ccoq +50 i ccauxq +i ccaux_ioq +515 ma xcku9p i ccintq + 1800 i ccbramq +i ccint_ioq + 600 i ccoq +50 i ccauxq +i ccaux_ioq +650 ma XCKU11P i ccintq + 1961 i ccbramq +i ccint_ioq + 654 i ccoq +55 i ccauxq +i ccaux_ioq +709 ma xcku13p i ccintq + 2242 i ccbramq +i ccint_ioq + 748 i ccoq +63 i ccauxq +i ccaux_ioq +810 ma xcku15p i ccintq + 3433 i ccbramq +i ccint_ioq +1145 i ccoq +96 i ccauxq +i ccaux_ioq + 1240 ma table 8: power supply ramp time symbol description min max units t vccint ramp time from gnd to 95% of v ccint .0.240ms t vccint_io ramp time from gnd to 95% of v ccint_io .0.240ms t vcco ramp time from gnd to 95% of v cco .0.240ms t vccaux ramp time from gnd to 95% of v ccaux .0.240ms t vccbram ramp time from gnd to 95% of v ccbram .0.240ms t mgtavcc ramp time from gnd to 95% of v mgtavcc .0.240ms t mgtavtt ramp time from gnd to 95% of v mgtavtt .0.240ms t mgtvccaux ramp time from gnd to 95% of v mgtvccaux .0.240ms s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 12 dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet th eir specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. table 9: selectio dc input and output levels for hd i/o banks (1)(2)(3) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma hstl_i ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 8.0 ?8.0 hstl_i_18 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 8.0 ?8.0 hsul_12 ?0.300 v ref ? 0.130 v ref +0.130 v cco + 0.300 20% v cco 80% v cco 0.1 ?0.1 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ? 0.400 note 4 note 4 lvcmos15 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 5 note 5 lvcmos18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 5 note 5 lvcmos25 ?0.300 0.700 1.700 v cco + 0.300 0.400 v cco ? 0.400 note 5 note 5 lvcmos33 ?0.300 0.800 2.000 3.400 0.400 v cco ? 0.400 note 5 note 5 lvttl ?0.300 0.800 2.000 3.400 0.400 2.400 note 5 note 5 sstl12 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 14.25 ?14.25 sstl135 ?0.300 v ref ? 0.090 v ref +0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 8.9 ?8.9 sstl135_ii ?0.300 v ref ? 0.090 v ref +0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 13.0 ?13.0 sstl15 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 8.9 ?8.9 sstl15_ii ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 13.0 ?13.0 sstl18_i ?0.300 v ref ? 0.125 v ref +0.125 v cco + 0.300 v cco /2?0.470 v cco /2 + 0.470 8.0 ?8.0 sstl18_ii ?0.300 v ref ? 0.125 v ref +0.125 v cco + 0.300 v cco /2?0.600 v cco /2 + 0.600 13.4 ?13.4 mipi_dphy_ dci_lp (6) ?0.300 0.550 0.880 v cco + 0.300 0.050 1.100 0.01 ?0.01 notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). 3. pod10 and pod12 dc input and output levels are shown in table 11 , table 15 , table 16 , and table 17 . 4. supported drive stre ngths of 4, 8, or 12 ma in hd i/o banks. 5. supported drive streng ths of 4, 8, 12, or 16 ma in hd i/o banks. 6. low-power option for mipi_dphy_dci. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 13 table 10: selectio dc input and output levels for hp i/o banks (1)(2)(3) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma hstl_i ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 5.8 ?5.8 hstl_i_12 ?0.300 v ref ? 0.080 v ref +0.080 v cco + 0.300 25% v cco 75% v cco 4.1 ?4.1 hstl_i_18 ?0.300 v ref ? 0.100 v ref +0.100 v cco + 0.300 0.400 v cco ? 0.400 6.2 ?6.2 hsul_12 ?0.300 v ref ? 0.130 v ref +0.130 v cco + 0.300 20% v cco 80% v cco 0.1 ?0.1 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ? 0.400 note 4 note 4 lvcmos15 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 5 note 5 lvcmos18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 5 note 5 lvdci_15 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 7.0 ?7.0 lvdci_18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 7.0 ?7.0 sstl12 ?0.300 v ref ? 0.100 v ref +0.100 v cco +0.300 v cco /2?0.150 v cco /2 + 0.150 8.0 ?8.0 sstl135 ?0.300 v ref ? 0.090 v ref +0.090 v cco +0.300 v cco /2?0.150 v cco /2 + 0.150 9.0 ?9.0 sstl15 ?0.300 v ref ? 0.100 v ref +0.100 v cco +0.300 v cco /2?0.175 v cco /2 + 0.175 10.0 ?10.0 sstl18_i ?0.300 v ref ? 0.125 v ref +0.125 v cco +0.300 v cco /2?0.470 v cco /2 + 0.470 7.0 ?7.0 mipi_dphy_ dci_lp (6) ?0.300 0.550 0.880 v cco + 0.300 0.050 1.100 0.01 ?0.01 notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). 3. pod10 and pod12 dc input and output levels are shown in table 11 , table 15 , table 16 , and table 17 . 4. supported drive streng ths of 2, 4, 6, or 8 ma in hp i/o banks. 5. supported drive strength s of 2, 4, 6, 8, or 12 ma in hp i/o banks. 6. low-power option for mipi_dphy_dci. table 11: dc input levels for single-ended pod10 and pod12 i/o standards (1)(2) i/o standard v il v ih v, min v, max v, min v, max pod10 ?0.300 v ref ? 0.068 v ref +0.068 v cco + 0.300 pod12 ?0.300 v ref ? 0.068 v ref +0.068 v cco + 0.300 notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 14 table 12: differential selectio dc input and output levels i/o standard v icm (v) (1) v id (v) (2) v ilhs (3) v ihhs (3) v ocm (v) (4) v od (v) (5) min typ max min typ max min max min typ max min typ max sub_lvds (8) 0.500 0.900 1.300 0.070 ? ? ? ? 0.700 0.900 1.100 0.100 0.150 0.200 lvpecl 0.300 1.200 1.425 0.100 0.350 0.600 ? ? ? ? ? ? ? ? slvs_400_18 0.070 0.200 0.330 0.140 ? 0.450 ? ? ? ? ? ? ? ? slvs_400_25 0.070 0.200 0.330 0.140 ? 0.450 ? ? ? ? ? ? ? ? mipi_dphy_ dci_hs (9) 0.070 0.330 0.070 ? ? ?0.040 0.460 0.150 0.200 0.250 0.140 0.200 0.270 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ihhs and v ilhs are the single-ended input high and low voltages, respectively. 4. v ocm is the output common mode voltage. 5. v od is the output differential voltage (q ? q ). 6. lvds_25 is specified in table 18 . 7. lvds is specified in table 19 . 8. only the sub_lvds receiver is supported in hd i/o banks. 9. high-speed option for mipi_dphy_dci. the v id maximum is aligned with the standard?s specification. a higher v id is acceptable as long as the v in specification is also met. table 13: complementary differential selectio dc in put and output levels for hd i/o banks i/o standard v icm (v) (1) v id (v) (2) v ol (v) (3) v oh (v) (4) i ol i oh min typ max min max max min ma ma diff_hstl_i 0.300 0.750 1.125 0.100 ? 0.400 v cco ? 0.400 8.0 ?8.0 diff_hstl_i_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ? 0.400 8.0 ?8.0 diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.1 ?0.1 diff_sstl12 0.300 0.600 0.850 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 14.25 ?14.25 diff_sstl135 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.9 ?8.9 diff_sstl135_ii 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 13.0 ?13.0 diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 8.9 ?8.9 diff_sstl15_ii 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 13.0 ?13.0 diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 8.0 ?8.0 diff_sstl18_ii 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.600 (v cco /2) + 0.600 13.4 ?13.4 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage. 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 15 table 14: complementary differential selectio dc in put and output levels for hp i/o banks (1) i/o standard v icm (v) (2) v id (v) (3) v ol (v) (4) v oh (v) (5) i ol i oh min typ max min max max min ma ma diff_hstl_i 0.680 v cco /2 (v cco /2) + 0.150 0.100 ? 0.400 v cco ? 0.400 5.8 ?5.8 diff_hstl_i_12 0.400 x v cco v cco /2 0.600 x v cco 0.100 ? 0.250 x v cco 0.750 x v cco 4.1 ?4.1 diff_hstl_i_18 (v cco /2) ? 0.175 v cco /2 (v cco /2) + 0.175 0.100 ? 0.400 v cco ? 0.400 6.2 ?6.2 diff_hsul_12 (v cco /2) ? 0.120 v cco /2 (v cco /2) + 0.120 0.100 ? 20% v cco 80% v cco 0.1 ?0.1 diff_sstl12 (v cco /2) ? 0.150 v cco /2 (v cco /2) + 0.150 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.0 ?8.0 diff_sstl135 (v cco /2) ? 0.150 v cco /2 (v cco /2) + 0.150 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 9.0 ?9.0 diff_sstl15 (v cco /2) ? 0.175 v cco /2 (v cco /2) + 0.175 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 10.0 ?10.0 diff_sstl18_i (v cco /2) ? 0.175 v cco /2 (v cco /2) + 0.175 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 7.0 ?7.0 notes: 1. diff_pod10 and diff_pod12 hp i/o ba nk specifications are shown in table 15 , table 16 , and table 17 . 2. v icm is the input common mode voltage. 3. v id is the input differential voltage. 4. v ol is the single-ended low-output voltage. 5. v oh is the single-ended high-output voltage. table 15: dc input levels for differentia l pod10 and pod12 i/o standards (1)(2) i/o standard v icm (v) v id (v) min typ max min max diff_pod10 0.63 0.70 0.77 0.14 ? diff_pod12 0.76 0.84 0.92 0.16 ? notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). table 16: dc output levels for sing le-ended and differential pod10 and pod12 standards (1)(2) symbol description v out min typ max units r ol pull-down resistance. v om_dc (as described in table 17 ) 364044 r oh pull-up resistance. v om_dc (as described in table 17 ) 364044 notes: 1. tested according to relevant specifications. 2. standards specified using the default i/o st andard configuration. for details, see the ultrascale architecture selectio resources user guide ( ug571 ). table 17: table 16 definitions for dc output levels for pod standards symbol description all speed grades units v om_dc dc output mid measurement level (for iv curve linearity). 0.8 x v cco v s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 16 lvds dc specifications (lvds_25) the lvds_25 standard is available in the hd i/o banks. see the ultrascale architectu re selectio resources user guide ( ug571 ) for more information. lvds dc specifications (lvds) the lvds standard is available in the hp i/o banks. see the ultrascale architecture selectio resources user guide ( ug571 ) for more information. table 18: lvds_25 dc specifications symbol dc parameter conditions min typ max units v cco (1) supply voltage. 2.375 2.500 2.625 v v idiff differential input voltage: (q ? q ), q = high (q ?q), q =high 100 350 600 (2) mv v icm input common-mode voltage. 0.300 1.200 1.500 v notes: 1. hd i/o banks only support lvds_25 inputs. lvds_25 inputs without internal termination have no v cco requirements. any v cco can be chosen as long as the inpu t voltage levels do not violate the recommended operating condition ( table 2 ) specification for the v in i/o pin voltage. 2. maximum v idiff value is specified for the maximum v icm specification. with a lower v icm , a higher v diff is tolerated only when the recommended operating cond itions and oversh oot/undershoot v in specifications are maintained. table 19: lvds dc specifications symbol dc parameter conditions min typ max units v cco (1) supply voltage. 1.710 1.800 1.890 v v odiff (2) differential output voltage: (q ? q ), q = high (q ?q), q =high r t =100 across q and q signals 247 350 600 mv v ocm (2) output common-mode voltage. r t =100 across q and q signals 1.000 1.250 1.425 v v idiff (3) differential input voltage: (q ? q ), q = high (q ?q), q =high 100 350 600 (3) mv v icm_dc (4) input common-mode voltage (dc coupling). 0.300 1.200 1.425 v v icm_ac (5) input common-mode voltage (ac coupling). 0.600 ? 1.100 v notes: 1. in hp i/o banks, when lvds is used with input-only functionality, it can be pl aced in a bank where the v cco levels are different from the specified level only if internal diff erential termination is not used. in this scenario, v cco must be chosen to ensure the input pin voltage levels do not violate the recommended operating condition ( table 2 ) specification for the v in i/o pin voltage. 2. v ocm and v odiff values are for lvds_pre_emphasis = false. 3. maximum v idiff value is specified for the maximum v icm specification. with a lower v icm , a higher v diff is tolerated only when the recommended operating cond itions and oversh oot/undershoot v in specifications are maintained. 4. input common mode voltage for dc coupled co nfigurations. equalization = eq_none (default). 5. external input common mode voltage specification for ac coupled configurations . equalization = eq_level0, eq_level1, eq_level2, eq_level3, eq_level4. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 17 ac switching characteristics all values represented in this data sheet are based on the speed specifications in the vivado? design suite as outlined in table 20 . switching characteristics are specified on a per-spee d-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance product specification these specifications are based on simulations only an d are typically available so on after device design specifications are frozen. although speed grades with this designation are consider ed relatively stable and conservative, some under-rep orting might still occur. preliminary product specification these specifications are based on complete es (engin eering sample) silicon characterization. devices and speed grades with this designation are intended to gi ve a better indication of the expected performance of production silicon. the probability of under-repo rting delays is greatly reduced as compared to advance data. product specification these specifications are released once enough producti on silicon of a particular device family member has been characterized to provide full correlation be tween specifications and devices over numerous production lots. there is no under-reporting of dela ys, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. testing of ac switching characteristics internal timing parameters are derived from meas uring internal test patt erns. all ac switching characteristics are representative of worst-case supply voltage and junction temperature conditions. for more specific, more precise, and worst-case guar anteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all kintex ultrascale+ fpgas. table 20: speed specification version by device 2016.1 device 1.04 xcku3p, xcku5p, xcku9p, XCKU11P, xcku13p, and xcku15p s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 18 speed grade designations since individual family members are produced at di fferent times, the migration from one category to another depends completely on the status of the fabrication process for each device. table 21 correlates the current status of the kintex ultrascale+ fpgas on a per speed grade basis. table 21: speed grade designations by device device speed grade, temperature ranges, and v ccint operating voltages advance preliminary production xcku3p -3e (v ccint = 0.90v) -2i (v ccint = 0.85v), -2le (v ccint = 0.85v) -1e (v ccint = 0.85v), -1i (v ccint = 0.85v), -1li (v ccint =0.85v) -2le (v ccint = 0.72v), -1li (v ccint =0.72v) xcku5p -3e (v ccint = 0.90v) -2i (v ccint = 0.85v), -2le (v ccint = 0.85v) -1e (v ccint = 0.85v), -1i (v ccint = 0.85v), -1li (v ccint =0.85v) -2le (v ccint = 0.72v), -1li (v ccint =0.72v) xcku9p -3e (v ccint = 0.90v) -2i (v ccint = 0.85v), -2le (v ccint = 0.85v) -1e (v ccint = 0.85v), -1i (v ccint = 0.85v), -1li (v ccint =0.85v) -2le (v ccint = 0.72v), -1li (v ccint =0.72v) XCKU11P -3e (v ccint = 0.90v) -2i (v ccint = 0.85v), -2le (v ccint = 0.85v) -1e (v ccint = 0.85v), -1i (v ccint = 0.85v), -1li (v ccint =0.85v) -2le (v ccint = 0.72v), -1li (v ccint =0.72v) xcku13p -3e (v ccint = 0.90v) -2i (v ccint = 0.85v), -2le (v ccint = 0.85v) -1e (v ccint = 0.85v), -1i (v ccint = 0.85v), -1li (v ccint =0.85v) -2le (v ccint = 0.72v), -1li (v ccint =0.72v) xcku15p -3e (v ccint = 0.90v) -2i (v ccint = 0.85v), -2le (v ccint = 0.85v) -1e (v ccint = 0.85v), -1i (v ccint = 0.85v), -1li (v ccint =0.85v) -2le (v ccint = 0.72v), -1li (v ccint =0.72v) s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 19 production silicon and software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with th e correct label (advance, prelimin ary, production). any labeling discrepancies are corrected in subseq uent speed specification releases. table 22 lists the production released kintex ultrascale+ fpgas, speed grade, and the minimum corresponding supported speed specification version an d vivado software revisions. the vivado software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. table 22: kintex ultrascale+ fpga device production software and speed sp ecification release device speed grade and v ccint operating voltages 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 xcku3p xcku5p xcku9p XCKU11P xcku13p xcku15p notes: 1. blank entries indicate a device and/or sp eed grade in advance or preliminary status. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 20 fpga logic performance characteristics this section provides the performance characte ristics of some common functions and designs implemented in kintex ultrascale+ fpgas. these values are subject to the same guidelines as the ac switching characteristics, page 17 . in each table, the i/o bank type is either high performance (hp) or high density (hd). table 23: lvds component mode performance description i/o bank type speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 lvds tx ddr (oserdes 4:1, 8:1) hp 1250 1250 1250 1250 1250 mb/s lvds tx sdr (oserdes 2:1, 4:1) hp 710 710 625 710 625 mb/s lvds rx ddr (iserdes 1:4, 1:8) (1) hp 1250 1250 1250 1250 1250 mb/s hd mb/s lvds rx sdr (iserdes 1:2, 1:4) (1) hp 710 710 625 710 625 mb/s hd mb/s notes: 1. lvds receivers are typically bounded with certain applications where specif ic dynamic phase-alignment (dpa) or phase-tracking algorithms are used to achieve maximum performance. table 24: lvds native mode performance (1) description i/o bank type speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 lvds tx ddr (tx_bitslice 4:1, 8:1) hp 1600 1600 1250 1600 1250 mb/s lvds tx sdr (tx_bitslice 2:1, 4:1) hp 800 800 625 800 625 mb/s lvds rx ddr (rx_bitslice 1:4, 1:8) (2) hp 1600 1600 1250 1600 1250 mb/s lvds rx sdr (rx_bitslice 1:2, 1:4) (2) hp 800 800 625 800 625 mb/s notes: 1. native mode is supported through the high-speed selectio interface wizard available with the vivado design suite. 2. lvds receivers are typically bounded with certain applications where specif ic dynamic phase-alignment (dpa) or phase-tracking algorithms are used to achieve maximum performance. table 25: lvds native-mode 1000base-x support (1) description i/o bank type speed grade and v ccint operating voltages 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 1000base-x hp yes notes: 1. 1000base-x support is based on the ieee standard for csma/cd access me thod and physical layer specifications (ieee std 802.3-2008). s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 21 table 26 provides the maximum data rates for applicable memory standards using the kintex ultrascale+ fpga memory phy. refer to memory interfaces for the complete list of memory interface standards supported and detailed specifications. the final perf ormance of the memory interface is determined through a complete design implemented in the viva do design suite, following guidelines in the ultrascale architecture pc b design guide ( ug583 ), electrical analysis, and ch aracterization of the system. table 26: maximum physical interface (phy ) rate for memory interfaces memory standard package dram type speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 ddr4 all ffv packages single rank component 2666 2666 2400 2400 2133 mb/s 1 rank dimm (1)(2) 2400 2400 2133 2133 1866 mb/s 2 rank dimm (1)(3) 2133 2133 1866 1866 1600 mb/s 4 rank dimm (1)(4) 1600 1600 1333 1333 n/a mb/s sfvb784 single rank component 2400 2400 2133 2133 1866 mb/s 1 rank dimm (1)(2) 2133 2133 1866 1866 1600 mb/s 2 rank dimm (1)(3) 1866 1866 1600 1600 1333 mb/s ddr3 all ffv packages single rank component 2133 2133 2133 2133 1866 mb/s 1 rank dimm (1)(2) 1866 1866 1866 1866 1600 mb/s 2 rank dimm (1)(3) 1600 1600 1600 1600 1333 mb/s 4 rank dimm (1)(4) 1066 1066 1066 1066 800 mb/s sfvb784 single rank component 1866 1866 1866 1866 1600 mb/s 1 rank dimm (1)(2) 1600 1600 1600 1600 1333 mb/s 2 rank dimm (1)(3) 1333 1333 1333 1333 1066 mb/s 4 rank dimm (1)(4) 800 800 800 800 606 mb/s ddr3l all ffv packages single rank component 1866 1866 1866 1866 1600 mb/s 1 rank dimm (1)(2) 1600 1600 1600 1600 1333 mb/s 2 rank dimm (1)(3) 1333 1333 1333 1333 1066 mb/s 4 rank dimm (1)(4) 800 800 800 800 606 mb/s sfvb784 single rank component 1600 1600 1600 1600 1600 mb/s 1 rank dimm (1)(2) 1333 1333 1333 1333 1333 mb/s 2 rank dimm (1)(3) 1066 1066 1066 1066 1066 mb/s 4 rank dimm (1)(4) 606 606 606 606 606 mb/s qdr ii+ all single rank component (5) 633 633 600 600 550 mhz rldram 3 all ffv packages single rank component 1200 1200 1066 1066 933 mhz sfvb784 single rank component 1066 1066 933 933 800 mhz qdr iv xp all single rank component (6) 1066 1066 1066 933 933 mhz lpddr3 all single rank component 1600 1600 1600 1600 1600 mb/s notes: 1. dual in-line memory module (dimm) incl udes rdimm, sodimm, udimm, and lrdimm. 2. includes: 1 rank 1 slot, ddp 2 rank, lrdimm 2 or 4 rank 1 slot. 3. includes: 2 rank 1 slot, 1 rank 2 slot, lrdimm 2 rank 2 slot. 4. includes: 2 rank 2 slot, 4 rank 1 slot. 5. the qdrii+ performance spec ifications are for burst-leng th 4 (bl = 4) implementations. 6. this memory interface is not production qua lified and specification is subject to change. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 22 iob pad input, output, and 3-state table 27 (high-density iob (hd)) and table 28 (high-performance iob (hp)) summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. ? t inbuf_delay_pad_i is the delay from iob pad through the inpu t buffer to the i-pin of an iob pad. the delay varies depending on the capa bility of the selectio input buffer. ? t outbuf_delay_o_pad is the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the ca pability of the selectio output buffer. ? t outbuf_delay_td_pad is the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies de pending on the selectio capability of the output buffer. in hp i/o banks, the internal dci termi nation turn-on time is always faster than t outbuf_delay_td_pad when the dcitermdisable pin is used. in hd i/o banks, the on-die termination turn-on time is always faster than t outbuf_delay_td_pad when the intermdisable pin is used. table 27: iob high density (hd) sw itching characteristics i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 diff_hstl_i_18_f 0.569 0.577 0.638 0.577 0.558 1.359 1.452 1.587 1.452 1.456 1.359 1.452 1.587 1.452 1.456 ns diff_hstl_i_18_s 0.569 0.577 0.638 0.577 0.558 1.359 1.452 1.587 1.452 1.456 1.359 1.452 1.587 1.452 1.456 ns diff_hstl_i_f 0.566 0.56 0.633 0.56 0.552 1.464 1.575 1.725 1.575 1.574 1.464 1.575 1.725 1.575 1.574 ns diff_hstl_i_s 0.566 0.56 0.633 0.56 0.552 1.464 1.575 1.725 1.575 1.574 1.464 1.575 1.725 1.575 1.574 ns diff_hsul_12_f 0.562 0.547 0.599 0.547 0.522 1.395 1.508 1.634 1.508 1.506 1.395 1.508 1.634 1.508 1.506 ns diff_hsul_12_s 0.562 0.547 0.599 0.547 0.522 1.395 1.508 1.634 1.508 1.506 1.395 1.508 1.634 1.508 1.506 ns diff_sstl12_f 0.566 0.552 0.609 0.552 0.522 1.463 1.561 1.704 1.561 1.555 1.463 1.561 1.704 1.561 1.555 ns diff_sstl12_s 0.566 0.552 0.609 0.552 0.522 1.707 1.747 1.909 1.747 1.716 1.707 1.747 1.909 1.747 1.716 ns diff_sstl135_f 0.577 0.560 0.613 0.56 0.527 1.473 1.590 1.728 1.590 1.585 1.473 1.590 1.728 1.590 1.585 ns diff_sstl135_ii_f 0.577 0.560 0.613 0.56 0.527 1.406 1.498 1.636 1.498 1.491 1.406 1.498 1.636 1.498 1.491 ns diff_sstl135_ii_s 0.577 0.560 0.613 0.56 0.527 1.576 1.649 1.789 1.649 1.618 1.576 1.649 1.789 1.649 1.618 ns diff_sstl135_s 0.577 0.560 0.613 0.56 0.527 1.817 1.887 2.046 1.887 1.846 1.817 1.887 2.046 1.887 1.846 ns diff_sstl15_f 0.566 0.560 0.633 0.56 0.552 1.474 1.592 1.734 1.592 1.597 1.474 1.592 1.734 1.592 1.597 ns diff_sstl15_ii_f 0.566 0.560 0.633 0.56 0.552 1.406 1.511 1.659 1.511 1.505 1.406 1.511 1.659 1.511 1.505 ns diff_sstl15_ii_s 0.566 0.560 0.633 0.56 0.552 1.618 1.700 1.856 1.700 1.668 1.618 1.700 1.856 1.700 1.668 ns diff_sstl15_s 0.566 0.560 0.633 0.56 0.552 1.734 1.804 1.957 1.804 1.775 1.734 1.804 1.957 1.804 1.775 ns diff_sstl18_ii_f 0.569 0.577 0.638 0.577 0.558 1.357 1.473 1.604 1.473 1.469 1.357 1.473 1.604 1.473 1.469 ns diff_sstl18_ii_s 0.569 0.577 0.638 0.577 0.558 1.511 1.629 1.784 1.629 1.616 1.511 1.629 1.784 1.629 1.616 ns diff_sstl18_i_f 0.569 0.577 0.638 0.577 0.558 1.335 1.431 1.563 1.431 1.429 1.335 1.431 1.563 1.431 1.429 ns diff_sstl18_i_s 0.569 0.577 0.638 0.577 0.558 1.692 1.802 1.961 1.802 1.760 1.692 1.802 1.961 1.802 1.760 ns hstl_i_18_f 0.596 0.606 0.668 0.606 0.571 1.359 1.452 1.587 1.452 1.456 1.359 1.452 1.587 1.452 1.456 ns hstl_i_18_s 0.596 0.606 0.668 0.606 0.571 1.359 1.452 1.587 1.452 1.456 1.359 1.452 1.587 1.452 1.456 ns hstl_i_f 0.597 0.601 0.604 0.601 0.566 1.464 1.575 1.725 1.575 1.574 1.464 1.575 1.725 1.575 1.574 ns hstl_i_s 0.597 0.601 0.604 0.601 0.566 1.464 1.575 1.725 1.575 1.574 1.464 1.575 1.725 1.575 1.574 ns hsul_12_f 0.604 0.598 0.615 0.598 0.538 1.395 1.508 1.634 1.508 1.506 1.395 1.508 1.634 1.508 1.506 ns hsul_12_s 0.604 0.598 0.615 0.598 0.538 1.395 1.508 1.634 1.508 1.506 1.395 1.508 1.634 1.508 1.506 ns s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 23 lvcmos12_f_12 0.515 0.558 0.618 0.558 0.568 1.465 1.574 1.733 1.574 1.566 1.465 1.574 1.733 1.574 1.566 ns lvcmos12_f_4 0.515 0.558 0.618 0.558 0.568 1.628 1.705 1.883 1.705 1.714 1.628 1.705 1.883 1.705 1.714 ns lvcmos12_f_8 0.515 0.558 0.618 0.558 0.568 1.480 1.540 1.690 1.540 1.533 1.480 1.540 1.690 1.540 1.533 ns lvcmos12_s_12 0.515 0.558 0.618 0.558 0.568 1.874 1.975 2.142 1.975 1.931 1.874 1.975 2.142 1.975 1.931 ns lvcmos12_s_4 0.515 0.558 0.618 0.558 0.568 1.935 1.959 2.162 1.959 1.949 1.935 1.959 2.162 1.959 1.949 ns lvcmos12_s_8 0.515 0.558 0.618 0.558 0.568 2.042 2.081 2.273 2.081 2.041 2.042 2.081 2.273 2.081 2.041 ns lvcmos15_f_12 0.468 0.513 0.588 0.513 0.530 1.374 1.422 1.573 1.422 1.439 1.374 1.422 1.573 1.422 1.439 ns lvcmos15_f_16 0.468 0.513 0.588 0.513 0.530 1.352 1.430 1.564 1.430 1.427 1.352 1.430 1.564 1.430 1.427 ns lvcmos15_f_4 0.468 0.513 0.588 0.513 0.530 1.539 1.626 1.747 1.626 1.636 1.539 1.626 1.747 1.626 1.636 ns lvcmos15_f_8 0.468 0.513 0.588 0.513 0.530 1.461 1.529 1.661 1.529 1.503 1.461 1.529 1.661 1.529 1.503 ns lvcmos15_s_12 0.468 0.513 0.588 0.513 0.530 1.778 1.859 1.999 1.859 1.823 1.778 1.859 1.999 1.859 1.823 ns lvcmos15_s_16 0.468 0.513 0.588 0.513 0.530 2.060 2.089 2.300 2.089 2.026 2.060 2.089 2.300 2.089 2.026 ns lvcmos15_s_4 0.468 0.513 0.588 0.513 0.530 2.160 2.204 2.368 2.204 2.115 2.160 2.204 2.368 2.204 2.115 ns lvcmos15_s_8 0.468 0.513 0.588 0.513 0.530 2.081 2.088 2.311 2.088 2.063 2.081 2.088 2.311 2.088 2.063 ns lvcmos18_f_12 0.437 0.502 0.512 0.502 0.497 1.393 1.487 1.618 1.487 1.460 1.393 1.487 1.618 1.487 1.460 ns lvcmos18_f_16 0.437 0.502 0.512 0.502 0.497 1.356 1.459 1.568 1.459 1.429 1.356 1.459 1.568 1.459 1.429 ns lvcmos18_f_4 0.437 0.502 0.512 0.502 0.497 1.572 1.650 1.780 1.650 1.634 1.572 1.650 1.780 1.650 1.634 ns lvcmos18_f_8 0.437 0.502 0.512 0.502 0.497 1.478 1.546 1.704 1.546 1.540 1.478 1.546 1.704 1.546 1.540 ns lvcmos18_s_12 0.437 0.502 0.512 0.502 0.497 1.993 2.038 2.232 2.038 1.999 1.993 2.038 2.232 2.038 1.999 ns lvcmos18_s_16 0.437 0.502 0.512 0.502 0.497 1.935 2.012 2.189 2.012 1.966 1.935 2.012 2.189 2.012 1.966 ns lvcmos18_s_4 0.437 0.502 0.512 0.502 0.497 2.123 2.154 2.358 2.154 2.100 2.123 2.154 2.358 2.154 2.100 ns lvcmos18_s_8 0.437 0.502 0.512 0.502 0.497 2.100 2.123 2.328 2.123 2.076 2.100 2.123 2.328 2.123 2.076 ns lvcmos25_f_12 0.516 0.542 0.588 0.542 0.539 1.961 2.012 2.296 2.012 2.001 1.961 2.012 2.296 2.012 2.001 ns lvcmos25_f_16 0.516 0.542 0.588 0.542 0.539 1.893 1.967 2.251 1.967 1.958 1.893 1.967 2.251 1.967 1.958 ns lvcmos25_f_4 0.516 0.542 0.588 0.542 0.539 2.100 2.213 2.413 2.213 2.155 2.100 2.213 2.413 2.213 2.155 ns lvcmos25_f_8 0.516 0.542 0.588 0.542 0.539 2.052 2.101 2.423 2.101 2.093 2.052 2.101 2.423 2.101 2.093 ns lvcmos25_s_12 0.516 0.542 0.588 0.542 0.539 2.455 2.589 2.878 2.589 2.501 2.455 2.589 2.878 2.589 2.501 ns lvcmos25_s_16 0.516 0.542 0.588 0.542 0.539 2.360 2.478 2.775 2.478 2.382 2.360 2.478 2.775 2.478 2.382 ns lvcmos25_s_4 0.516 0.542 0.588 0.542 0.539 2.622 2.723 3.016 2.723 2.630 2.622 2.723 3.016 2.723 2.630 ns lvcmos25_s_8 0.516 0.542 0.588 0.542 0.539 2.538 2.643 2.943 2.643 2.567 2.538 2.643 2.943 2.643 2.567 ns lvcmos33_f_12 0.577 0.622 0.675 0.622 0.624 1.942 2.047 2.248 2.047 2.024 1.942 2.047 2.248 2.047 2.024 ns lvcmos33_f_16 0.577 0.622 0.675 0.622 0.624 1.976 2.072 2.266 2.072 2.048 1.976 2.072 2.266 2.072 2.048 ns lvcmos33_f_4 0.577 0.622 0.675 0.622 0.624 1.925 2.049 2.232 2.049 2.019 1.925 2.049 2.232 2.049 2.019 ns lvcmos33_f_8 0.577 0.622 0.675 0.622 0.624 2.101 2.189 2.375 2.189 2.149 2.101 2.189 2.375 2.189 2.149 ns lvcmos33_s_12 0.577 0.622 0.675 0.622 0.624 2.450 2.533 2.856 2.533 2.515 2.450 2.533 2.856 2.533 2.515 ns lvcmos33_s_16 0.577 0.622 0.675 0.622 0.624 2.424 2.495 2.782 2.495 2.430 2.424 2.495 2.782 2.495 2.430 ns lvcmos33_s_4 0.577 0.622 0.675 0.622 0.624 2.632 2.684 2.991 2.684 2.613 2.632 2.684 2.991 2.684 2.613 ns lvcmos33_s_8 0.577 0.622 0.675 0.622 0.624 2.561 2.644 2.946 2.644 2.578 2.561 2.644 2.946 2.644 2.578 ns lvds_25 0.597 0.587 0.671 0.587 0.598 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a ns lvpecl 0.597 0.587 0.671 0.587 0.598 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a ns lvttl_f_12 0.577 0.622 0.675 0.622 0.624 1.942 2.047 2.248 2.047 2.024 1.942 2.047 2.248 2.047 2.024 ns table 27: iob high density (hd) sw itching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 24 lvttl_f_16 0.577 0.622 0.675 0.622 0.624 1.994 2.144 2.379 2.144 2.081 1.994 2.144 2.379 2.144 2.081 ns lvttl_f_4 0.577 0.622 0.675 0.622 0.624 1.925 2.049 2.232 2.049 2.019 1.925 2.049 2.232 2.049 2.019 ns lvttl_f_8 0.577 0.622 0.675 0.622 0.624 2.093 2.190 2.365 2.190 2.144 2.093 2.190 2.365 2.190 2.144 ns lvttl_s_12 0.577 0.622 0.675 0.622 0.624 2.450 2.533 2.856 2.533 2.515 2.450 2.533 2.856 2.533 2.515 ns lvttl_s_16 0.577 0.622 0.675 0.622 0.624 2.424 2.495 2.782 2.495 2.430 2.424 2.495 2.782 2.495 2.430 ns lvttl_s_4 0.577 0.622 0.675 0.622 0.624 2.632 2.684 2.991 2.684 2.613 2.632 2.684 2.991 2.684 2.613 ns lvttl_s_8 0.577 0.622 0.675 0.622 0.624 2.561 2.644 2.946 2.644 2.578 2.561 2.644 2.946 2.644 2.578 ns slvs_400_25 0.597 0.587 0.671 0.587 0.598 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a ns sstl12_f 0.604 0.598 0.615 0.598 0.538 1.463 1.561 1.704 1.561 1.555 1.463 1.561 1.704 1.561 1.555 ns sstl12_s 0.604 0.598 0.615 0.598 0.538 1.707 1.747 1.909 1.747 1.716 1.707 1.747 1.909 1.747 1.716 ns sstl135_f 0.605 0.598 0.642 0.598 0.552 1.473 1.590 1.728 1.59 1.585 1.473 1.590 1.728 1.590 1.585 ns sstl135_ii_f 0.605 0.598 0.642 0.598 0.552 1.406 1.498 1.636 1.498 1.491 1.406 1.498 1.636 1.498 1.491 ns sstl135_ii_s 0.605 0.598 0.642 0.598 0.552 1.576 1.649 1.789 1.649 1.618 1.576 1.649 1.789 1.649 1.618 ns sstl135_s 0.605 0.598 0.642 0.598 0.552 1.817 1.887 2.046 1.887 1.846 1.817 1.887 2.046 1.887 1.846 ns sstl15_f 0.597 0.601 0.604 0.601 0.566 1.474 1.592 1.734 1.592 1.597 1.474 1.592 1.734 1.592 1.597 ns sstl15_ii_f 0.597 0.601 0.604 0.601 0.566 1.406 1.511 1.659 1.511 1.505 1.406 1.511 1.659 1.511 1.505 ns sstl15_ii_s 0.597 0.601 0.604 0.601 0.566 1.618 1.700 1.856 1.700 1.668 1.618 1.700 1.856 1.700 1.668 ns sstl15_s 0.597 0.601 0.604 0.601 0.566 1.734 1.804 1.957 1.804 1.775 1.734 1.804 1.957 1.804 1.775 ns sstl18_ii_f 0.596 0.606 0.668 0.606 0.571 1.357 1.473 1.604 1.473 1.469 1.357 1.473 1.604 1.473 1.469 ns sstl18_ii_s 0.596 0.606 0.668 0.606 0.571 1.511 1.629 1.784 1.629 1.616 1.511 1.629 1.784 1.629 1.616 ns sstl18_i_f 0.596 0.606 0.668 0.606 0.571 1.335 1.431 1.563 1.431 1.429 1.335 1.431 1.563 1.431 1.429 ns sstl18_i_s 0.596 0.606 0.668 0.606 0.571 1.692 1.802 1.961 1.802 1.76 1.692 1.802 1.961 1.802 1.760 ns sub_lvds 0.638 0.600 0.626 0.600 0.579 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a ns table 27: iob high density (hd) sw itching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 25 table 28: iob high performance (hp) switching characteristics i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 diff_hstl_i_12_f 0.277 0.335 0.342 0.335 0.321 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns diff_hstl_i_12_m 0.277 0.335 0.342 0.335 0.321 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns diff_hstl_i_12_s 0.277 0.335 0.342 0.335 0.321 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns diff_hstl_i_18_f 0.285 0.314 0.334 0.314 0.328 0.388 0.396 0.413 0.396 0.388 0.388 0.396 0.413 0.396 0.388 ns diff_hstl_i_18_m 0.285 0.314 0.334 0.314 0.328 0.388 0.393 0.413 0.393 0.389 0.388 0.393 0.413 0.393 0.389 ns diff_hstl_i_18_s 0.285 0.314 0.334 0.314 0.328 0.388 0.394 0.413 0.391 0.387 0.388 0.394 0.413 0.391 0.387 ns diff_hstl_i_dci_12_f 0.277 0.335 0.342 0.335 0.321 0.422 0.420 0.444 0.421 0.414 0.422 0.420 0.444 0.421 0.414 ns diff_hstl_i_dci_12_m 0.277 0.335 0.342 0.335 0.321 0.422 0.420 0.444 0.422 0.412 0.422 0.420 0.444 0.422 0.412 ns diff_hstl_i_dci_12_s 0.277 0.335 0.342 0.335 0.321 0.422 0.421 0.442 0.421 0.412 0.422 0.421 0.442 0.421 0.412 ns diff_hstl_i_dci_18_f 0.284 0.314 0.331 0.314 0.331 0.418 0.425 0.440 0.424 0.417 0.418 0.425 0.440 0.424 0.417 ns diff_hstl_i_dci_18_m 0.284 0.314 0.331 0.314 0.331 0.418 0.424 0.443 0.423 0.416 0.418 0.424 0.443 0.423 0.416 ns diff_hstl_i_dci_18_s 0.284 0.314 0.331 0.314 0.331 0.418 0.424 0.443 0.424 0.417 0.418 0.424 0.443 0.424 0.417 ns diff_hstl_i_dci_f 0.294 0.313 0.330 0.313 0.320 0.420 0.423 0.438 0.421 0.415 0.420 0.423 0.438 0.421 0.415 ns diff_hstl_i_dci_m 0.294 0.313 0.330 0.313 0.320 0.420 0.423 0.440 0.423 0.416 0.420 0.423 0.440 0.423 0.416 ns diff_hstl_i_dci_s 0.294 0.313 0.330 0.313 0.320 0.420 0.421 0.440 0.417 0.414 0.420 0.421 0.440 0.417 0.414 ns diff_hstl_i_f 0.295 0.330 0.341 0.330 0.320 0.393 0.391 0.411 0.394 0.385 0.393 0.391 0.411 0.394 0.385 ns diff_hstl_i_m 0.295 0.330 0.341 0.330 0.320 0.392 0.393 0.413 0.397 0.386 0.392 0.393 0.413 0.397 0.386 ns diff_hstl_i_s 0.295 0.330 0.341 0.330 0.320 0.393 0.393 0.413 0.394 0.384 0.393 0.393 0.413 0.394 0.384 ns diff_hsul_12_dci_f 0.283 0.327 0.344 0.327 0.317 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns diff_hsul_12_dci_m 0.283 0.327 0.344 0.327 0.317 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns diff_hsul_12_dci_s 0.283 0.327 0.344 0.327 0.317 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns diff_hsul_12_f 0.277 0.335 0.342 0.335 0.321 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns diff_hsul_12_m 0.277 0.335 0.342 0.335 0.321 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns diff_hsul_12_s 0.277 0.335 0.342 0.335 0.321 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns diff_pod10_dci_f 0.286 0.325 0.340 0.325 0.334 0.438 0.431 0.451 0.431 0.418 0.438 0.431 0.451 0.431 0.418 ns diff_pod10_dci_m 0.286 0.325 0.340 0.325 0.334 0.592 0.627 0.660 0.627 0.622 0.592 0.627 0.660 0.627 0.622 ns diff_pod10_dci_s 0.286 0.325 0.340 0.325 0.334 0.823 0.900 0.974 0.900 0.888 0.823 0.900 0.974 0.900 0.888 ns diff_pod10_f 0.277 0.314 0.331 0.314 0.317 0.412 0.406 0.426 0.406 0.392 0.412 0.406 0.426 0.406 0.392 ns diff_pod10_m 0.277 0.314 0.331 0.314 0.317 0.570 0.593 0.627 0.593 0.588 0.570 0.593 0.627 0.593 0.588 ns diff_pod10_s 0.277 0.314 0.331 0.314 0.317 0.800 0.853 0.914 0.853 0.835 0.800 0.853 0.914 0.853 0.835 ns diff_pod12_dci_f 0.275 0.314 0.333 0.314 0.318 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns diff_pod12_dci_m 0.275 0.314 0.333 0.314 0.318 0.586 0.628 0.662 0.628 0.623 0.586 0.628 0.662 0.628 0.623 ns diff_pod12_dci_s 0.275 0.314 0.333 0.314 0.318 0.813 0.899 0.959 0.899 0.892 0.813 0.899 0.959 0.899 0.892 ns diff_pod12_f 0.275 0.323 0.341 0.323 0.316 0.402 0.396 0.414 0.395 0.383 0.402 0.396 0.414 0.395 0.383 ns diff_pod12_m 0.275 0.323 0.341 0.323 0.316 0.562 0.595 0.629 0.595 0.589 0.562 0.595 0.629 0.595 0.589 ns diff_pod12_s 0.275 0.323 0.341 0.323 0.316 0.789 0.844 0.899 0.844 0.835 0.789 0.844 0.899 0.844 0.835 ns diff_sstl12_dci_f 0.283 0.327 0.344 0.327 0.317 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns diff_sstl12_dci_m 0.283 0.327 0.344 0.327 0.317 0.584 0.630 0.664 0.628 0.624 0.584 0.630 0.664 0.628 0.624 ns diff_sstl12_dci_s 0.283 0.327 0.344 0.327 0.317 0.813 0.899 0.959 0.899 0.892 0.813 0.899 0.959 0.899 0.892 ns diff_sstl12_f 0.277 0.335 0.342 0.335 0.321 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns diff_sstl12_m 0.277 0.335 0.342 0.335 0.321 0.561 0.597 0.631 0.597 0.591 0.561 0.597 0.631 0.597 0.591 ns s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 26 diff_sstl12_s 0.277 0.335 0.342 0.335 0.321 0.789 0.844 0.899 0.844 0.835 0.789 0.844 0.899 0.844 0.835 ns diff_sstl135_dci_f 0.278 0.312 0.339 0.312 0.319 0.426 0.420 0.439 0.422 0.414 0.426 0.420 0.439 0.422 0.414 ns diff_sstl135_dci_m 0.278 0.312 0.339 0.312 0.319 0.586 0.630 0.666 0.630 0.626 0.586 0.630 0.666 0.630 0.626 ns diff_sstl135_dci_s 0.278 0.312 0.339 0.312 0.319 0.814 0.902 0.966 0.895 0.896 0.814 0.902 0.966 0.895 0.896 ns diff_sstl135_f 0.289 0.313 0.336 0.313 0.315 0.397 0.392 0.412 0.394 0.385 0.397 0.392 0.412 0.394 0.385 ns diff_sstl135_m 0.289 0.313 0.336 0.313 0.315 0.565 0.599 0.633 0.598 0.593 0.565 0.599 0.633 0.598 0.593 ns diff_sstl135_s 0.289 0.313 0.336 0.313 0.315 0.789 0.850 0.907 0.849 0.841 0.789 0.850 0.907 0.849 0.841 ns diff_sstl15_dci_f 0.294 0.313 0.330 0.313 0.320 0.424 0.421 0.439 0.423 0.422 0.424 0.421 0.439 0.423 0.422 ns diff_sstl15_dci_m 0.294 0.313 0.330 0.313 0.320 0.591 0.632 0.667 0.632 0.627 0.591 0.632 0.667 0.632 0.627 ns diff_sstl15_dci_s 0.294 0.313 0.330 0.313 0.320 0.816 0.906 0.971 0.906 0.898 0.816 0.906 0.971 0.906 0.898 ns diff_sstl15_f 0.295 0.330 0.341 0.330 0.320 0.393 0.392 0.412 0.392 0.386 0.393 0.392 0.412 0.392 0.386 ns diff_sstl15_m 0.295 0.330 0.341 0.330 0.320 0.564 0.598 0.633 0.598 0.592 0.564 0.598 0.633 0.598 0.592 ns diff_sstl15_s 0.295 0.330 0.341 0.330 0.320 0.790 0.853 0.910 0.850 0.844 0.790 0.853 0.910 0.850 0.844 ns diff_sstl18_i_dci_f 0.284 0.314 0.331 0.314 0.331 0.418 0.425 0.440 0.424 0.416 0.418 0.425 0.440 0.424 0.416 ns diff_sstl18_i_dci_m 0.284 0.314 0.331 0.314 0.331 0.593 0.633 0.670 0.634 0.629 0.593 0.633 0.670 0.634 0.629 ns diff_sstl18_i_dci_s 0.284 0.314 0.331 0.314 0.331 0.821 0.910 0.978 0.911 0.903 0.821 0.910 0.978 0.911 0.903 ns diff_sstl18_i_f 0.285 0.314 0.334 0.314 0.328 0.388 0.395 0.415 0.392 0.387 0.388 0.395 0.415 0.392 0.387 ns diff_sstl18_i_m 0.285 0.314 0.334 0.314 0.328 0.567 0.603 0.638 0.603 0.596 0.567 0.603 0.638 0.603 0.596 ns diff_sstl18_i_s 0.285 0.314 0.334 0.314 0.328 0.794 0.861 0.920 0.860 0.851 0.794 0.861 0.920 0.860 0.851 ns hslvdci_15_f 0.343 0.364 0.384 0.364 0.360 0.424 0.422 0.440 0.421 0.418 0.424 0.422 0.440 0.421 0.418 ns hslvdci_15_m 0.343 0.364 0.384 0.364 0.360 0.424 0.420 0.441 0.424 0.413 0.424 0.420 0.441 0.424 0.413 ns hslvdci_15_s 0.343 0.364 0.384 0.364 0.360 0.424 0.421 0.440 0.421 0.417 0.424 0.421 0.440 0.421 0.417 ns hslvdci_18_f 0.343 0.365 0.386 0.365 0.361 0.420 0.425 0.440 0.424 0.416 0.420 0.425 0.440 0.424 0.416 ns hslvdci_18_m 0.343 0.365 0.386 0.365 0.361 0.423 0.424 0.440 0.423 0.418 0.423 0.424 0.440 0.423 0.418 ns hslvdci_18_s 0.343 0.365 0.386 0.365 0.361 0.420 0.423 0.443 0.425 0.414 0.420 0.423 0.443 0.425 0.414 ns hstl_i_12_f 0.342 0.363 0.384 0.363 0.360 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns hstl_i_12_m 0.342 0.363 0.384 0.363 0.360 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns hstl_i_12_s 0.342 0.363 0.384 0.363 0.360 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns hstl_i_18_f 0.343 0.365 0.386 0.365 0.361 0.388 0.396 0.413 0.396 0.388 0.388 0.396 0.413 0.396 0.388 ns hstl_i_18_m 0.343 0.365 0.386 0.365 0.361 0.388 0.393 0.413 0.393 0.389 0.388 0.393 0.413 0.393 0.389 ns hstl_i_18_s 0.343 0.365 0.386 0.365 0.361 0.388 0.394 0.413 0.391 0.387 0.388 0.394 0.413 0.391 0.387 ns hstl_i_dci_12_f 0.342 0.363 0.384 0.363 0.360 0.422 0.420 0.444 0.421 0.414 0.422 0.420 0.444 0.421 0.414 ns hstl_i_dci_12_m 0.342 0.363 0.384 0.363 0.360 0.422 0.420 0.444 0.422 0.412 0.422 0.420 0.444 0.422 0.412 ns hstl_i_dci_12_s 0.342 0.363 0.384 0.363 0.360 0.422 0.421 0.442 0.421 0.412 0.422 0.421 0.442 0.421 0.412 ns hstl_i_dci_18_f 0.343 0.365 0.386 0.365 0.361 0.418 0.425 0.440 0.424 0.417 0.418 0.425 0.440 0.424 0.417 ns hstl_i_dci_18_m 0.343 0.365 0.386 0.365 0.361 0.418 0.424 0.443 0.423 0.416 0.418 0.424 0.443 0.423 0.416 ns hstl_i_dci_18_s 0.343 0.365 0.386 0.365 0.361 0.418 0.424 0.443 0.424 0.417 0.418 0.424 0.443 0.424 0.417 ns hstl_i_dci_f 0.343 0.364 0.384 0.364 0.360 0.420 0.423 0.438 0.421 0.415 0.420 0.423 0.438 0.421 0.415 ns hstl_i_dci_m 0.343 0.364 0.384 0.364 0.360 0.420 0.423 0.440 0.423 0.416 0.420 0.423 0.440 0.423 0.416 ns hstl_i_dci_s 0.343 0.364 0.384 0.364 0.360 0.420 0.421 0.440 0.417 0.414 0.420 0.421 0.440 0.417 0.414 ns hstl_i_f 0.342 0.363 0.384 0.363 0.360 0.393 0.391 0.411 0.394 0.385 0.393 0.391 0.411 0.394 0.385 ns table 28: iob high performance (hp) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 27 hstl_i_m 0.342 0.363 0.384 0.363 0.360 0.392 0.393 0.413 0.397 0.386 0.392 0.393 0.413 0.397 0.386 ns hstl_i_s 0.342 0.363 0.384 0.363 0.360 0.393 0.393 0.413 0.394 0.384 0.393 0.393 0.413 0.394 0.384 ns hsul_12_dci_f 0.343 0.363 0.384 0.363 0.360 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns hsul_12_dci_m 0.343 0.363 0.384 0.363 0.360 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns hsul_12_dci_s 0.343 0.363 0.384 0.363 0.360 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns hsul_12_f 0.342 0.363 0.384 0.363 0.360 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns hsul_12_m 0.342 0.363 0.384 0.363 0.360 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns hsul_12_s 0.342 0.363 0.384 0.363 0.360 0.402 0.395 0.414 0.395 0.383 0.402 0.395 0.414 0.395 0.383 ns lvcmos12_f_2 0.476 0.552 0.600 0.552 0.557 0.865 0.841 0.867 0.839 0.820 0.865 0.841 0.867 0.839 0.820 ns lvcmos12_f_4 0.476 0.552 0.600 0.552 0.557 0.640 0.642 0.665 0.635 0.624 0.640 0.642 0.665 0.635 0.624 ns lvcmos12_f_6 0.476 0.552 0.600 0.552 0.557 0.533 0.515 0.540 0.515 0.502 0.533 0.515 0.540 0.515 0.502 ns lvcmos12_f_8 0.476 0.552 0.600 0.552 0.557 0.476 0.472 0.498 0.477 0.461 0.476 0.472 0.498 0.477 0.461 ns lvcmos12_m_2 0.476 0.552 0.600 0.552 0.557 0.904 0.899 0.923 0.893 0.881 0.904 0.899 0.923 0.893 0.881 ns lvcmos12_m_4 0.476 0.552 0.600 0.552 0.557 0.740 0.741 0.773 0.741 0.733 0.740 0.741 0.773 0.741 0.733 ns lvcmos12_m_6 0.476 0.552 0.600 0.552 0.557 0.634 0.655 0.690 0.657 0.648 0.634 0.655 0.690 0.657 0.648 ns lvcmos12_m_8 0.476 0.552 0.600 0.552 0.557 0.633 0.672 0.712 0.672 0.665 0.633 0.672 0.712 0.672 0.665 ns lvcmos12_s_2 0.476 0.552 0.600 0.552 0.557 0.974 0.976 1.022 0.976 0.963 0.974 0.976 1.022 0.976 0.963 ns lvcmos12_s_4 0.476 0.552 0.600 0.552 0.557 0.861 0.902 0.956 0.902 0.888 0.861 0.902 0.956 0.902 0.888 ns lvcmos12_s_6 0.476 0.552 0.600 0.552 0.557 0.821 0.890 0.943 0.890 0.876 0.821 0.890 0.943 0.890 0.876 ns lvcmos12_s_8 0.476 0.552 0.600 0.552 0.557 0.871 0.947 1.020 0.947 0.939 0.871 0.947 1.020 0.947 0.939 ns lvcmos15_f_12 0.395 0.443 0.478 0.443 0.439 0.422 0.417 0.436 0.417 0.408 0.422 0.417 0.436 0.417 0.408 ns lvcmos15_f_2 0.395 0.443 0.478 0.443 0.439 0.847 0.837 0.861 0.832 0.819 0.847 0.837 0.861 0.832 0.819 ns lvcmos15_f_4 0.395 0.443 0.478 0.443 0.439 0.637 0.633 0.658 0.633 0.621 0.637 0.633 0.658 0.633 0.621 ns lvcmos15_f_6 0.395 0.443 0.478 0.443 0.439 0.517 0.511 0.532 0.511 0.501 0.517 0.511 0.532 0.511 0.501 ns lvcmos15_f_8 0.395 0.443 0.478 0.443 0.439 0.472 0.469 0.488 0.468 0.457 0.472 0.469 0.488 0.468 0.457 ns lvcmos15_m_12 0.395 0.443 0.478 0.443 0.439 0.669 0.73 0.775 0.73 0.723 0.669 0.73 0.775 0.73 0.723 ns lvcmos15_m_2 0.395 0.443 0.478 0.443 0.439 0.898 0.895 0.93 0.895 0.883 0.898 0.895 0.93 0.895 0.883 ns lvcmos15_m_4 0.395 0.443 0.478 0.443 0.439 0.726 0.743 0.774 0.743 0.731 0.726 0.743 0.774 0.743 0.731 ns lvcmos15_m_6 0.395 0.443 0.478 0.443 0.439 0.633 0.658 0.691 0.659 0.642 0.633 0.658 0.691 0.659 0.642 ns lvcmos15_m_8 0.395 0.443 0.478 0.443 0.439 0.635 0.673 0.714 0.673 0.669 0.635 0.673 0.714 0.673 0.669 ns lvcmos15_s_12 0.395 0.443 0.478 0.443 0.439 1.002 1.119 1.216 1.122 1.112 1.002 1.119 1.216 1.122 1.112 ns lvcmos15_s_2 0.395 0.443 0.478 0.443 0.439 0.967 0.979 1.022 0.977 0.965 0.967 0.979 1.022 0.977 0.965 ns lvcmos15_s_4 0.395 0.443 0.478 0.443 0.439 0.861 0.907 0.959 0.907 0.894 0.861 0.907 0.959 0.907 0.894 ns lvcmos15_s_6 0.395 0.443 0.478 0.443 0.439 0.825 0.898 0.950 0.898 0.885 0.825 0.898 0.950 0.898 0.885 ns lvcmos15_s_8 0.395 0.443 0.478 0.443 0.439 0.871 0.955 1.026 0.953 0.943 0.871 0.955 1.026 0.953 0.943 ns lvcmos18_f_12 0.352 0.388 0.414 0.388 0.377 0.412 0.418 0.440 0.418 0.410 0.412 0.418 0.440 0.418 0.410 ns lvcmos18_f_2 0.352 0.388 0.414 0.388 0.377 0.850 0.841 0.865 0.841 0.828 0.850 0.841 0.865 0.841 0.828 ns lvcmos18_f_4 0.352 0.388 0.414 0.388 0.377 0.643 0.637 0.660 0.637 0.624 0.643 0.637 0.660 0.637 0.624 ns lvcmos18_f_6 0.352 0.388 0.414 0.388 0.377 0.507 0.506 0.532 0.506 0.501 0.507 0.506 0.532 0.506 0.501 ns lvcmos18_f_8 0.352 0.388 0.414 0.388 0.377 0.468 0.468 0.491 0.468 0.459 0.468 0.468 0.491 0.468 0.459 ns lvcmos18_m_12 0.352 0.388 0.414 0.388 0.377 0.681 0.734 0.779 0.734 0.727 0.681 0.734 0.779 0.734 0.727 ns table 28: iob high performance (hp) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 28 lvcmos18_m_2 0.352 0.388 0.414 0.388 0.377 0.902 0.899 0.927 0.899 0.884 0.902 0.899 0.927 0.899 0.884 ns lvcmos18_m_4 0.352 0.388 0.414 0.388 0.377 0.731 0.745 0.778 0.745 0.731 0.731 0.745 0.778 0.745 0.731 ns lvcmos18_m_6 0.352 0.388 0.414 0.388 0.377 0.638 0.659 0.696 0.664 0.653 0.638 0.659 0.696 0.664 0.653 ns lvcmos18_m_8 0.352 0.388 0.414 0.388 0.377 0.632 0.678 0.717 0.678 0.667 0.632 0.678 0.717 0.678 0.667 ns lvcmos18_s_12 0.352 0.388 0.414 0.388 0.377 1.015 1.130 1.224 1.130 1.119 1.015 1.130 1.224 1.130 1.119 ns lvcmos18_s_2 0.352 0.388 0.414 0.388 0.377 0.967 0.983 1.024 0.984 0.967 0.967 0.983 1.024 0.984 0.967 ns lvcmos18_s_4 0.352 0.388 0.414 0.388 0.377 0.864 0.910 0.964 0.910 0.897 0.864 0.910 0.964 0.910 0.897 ns lvcmos18_s_6 0.352 0.388 0.414 0.388 0.377 0.836 0.900 0.957 0.900 0.888 0.836 0.900 0.957 0.900 0.888 ns lvcmos18_s_8 0.352 0.388 0.414 0.388 0.377 0.881 0.959 1.033 0.959 0.948 0.881 0.959 1.033 0.959 0.948 ns lvdci_15_f 0.392 0.436 0.476 0.436 0.437 0.424 0.422 0.441 0.418 0.415 0.424 0.422 0.441 0.418 0.415 ns lvdci_15_m 0.392 0.436 0.476 0.436 0.437 0.591 0.632 0.666 0.632 0.628 0.591 0.632 0.666 0.632 0.628 ns lvdci_15_s 0.392 0.436 0.476 0.436 0.437 0.815 0.906 0.972 0.905 0.898 0.815 0.906 0.972 0.905 0.898 ns lvdci_18_f 0.346 0.376 0.407 0.376 0.374 0.418 0.425 0.443 0.425 0.418 0.418 0.425 0.443 0.425 0.418 ns lvdci_18_m 0.346 0.376 0.407 0.376 0.374 0.594 0.633 0.670 0.633 0.628 0.594 0.633 0.670 0.633 0.628 ns lvdci_18_s 0.346 0.376 0.407 0.376 0.374 0.821 0.908 0.978 0.908 0.902 0.821 0.908 0.978 0.908 0.902 ns lvds 0.315 0.352 0.406 0.352 0.348 0.392 0.404 0.425 0.404 0.396 0.392 0.404 0.425 0.404 0.396 ns mipi_dphy_dci_hs 0.305 0.317 0.342 0.317 0.319 0.429 0.434 0.452 0.434 0.427 n/a n/a n/a n/a n/a ns mipi_dphy_dci_lp 8.477 8.423 8.777 8.415 8.698 1.627 1.604 1.642 1.604 1.583 n/a n/a n/a n/a n/a ns pod10_dci_f 0.342 0.363 0.384 0.363 0.360 0.438 0.431 0.451 0.431 0.418 0.438 0.431 0.451 0.431 0.418 ns pod10_dci_m 0.342 0.363 0.384 0.363 0.360 0.592 0.627 0.660 0.627 0.622 0.592 0.627 0.660 0.627 0.622 ns pod10_dci_s 0.342 0.363 0.384 0.363 0.360 0.823 0.900 0.974 0.900 0.888 0.823 0.900 0.974 0.900 0.888 ns pod10_f 0.343 0.363 0.384 0.363 0.360 0.412 0.406 0.426 0.406 0.392 0.412 0.406 0.426 0.406 0.392 ns pod10_m 0.343 0.363 0.384 0.363 0.360 0.570 0.593 0.627 0.593 0.588 0.570 0.593 0.627 0.593 0.588 ns pod10_s 0.343 0.363 0.384 0.363 0.360 0.800 0.853 0.914 0.853 0.835 0.800 0.853 0.914 0.853 0.835 ns pod12_dci_f 0.343 0.364 0.386 0.364 0.360 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns pod12_dci_m 0.343 0.364 0.386 0.364 0.360 0.586 0.628 0.662 0.628 0.623 0.586 0.628 0.662 0.628 0.623 ns pod12_dci_s 0.343 0.364 0.386 0.364 0.360 0.813 0.899 0.959 0.899 0.892 0.813 0.899 0.959 0.899 0.892 ns pod12_f 0.343 0.364 0.386 0.364 0.360 0.402 0.396 0.414 0.395 0.383 0.402 0.396 0.414 0.395 0.383 ns pod12_m 0.343 0.364 0.386 0.364 0.360 0.562 0.595 0.629 0.595 0.589 0.562 0.595 0.629 0.595 0.589 ns pod12_s 0.343 0.364 0.386 0.364 0.360 0.789 0.844 0.899 0.844 0.835 0.789 0.844 0.899 0.844 0.835 ns slvs_400_18 0.315 0.352 0.406 0.352 0.348 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a ns sstl12_dci_f 0.331 0.366 0.384 0.366 0.350 0.428 0.421 0.440 0.421 0.412 0.428 0.421 0.440 0.421 0.412 ns sstl12_dci_m 0.331 0.366 0.384 0.366 0.350 0.584 0.630 0.664 0.628 0.624 0.584 0.630 0.664 0.628 0.624 ns sstl12_dci_s 0.331 0.366 0.384 0.366 0.350 0.813 0.899 0.959 0.899 0.892 0.813 0.899 0.959 0.899 0.892 ns sstl12_f 0.333 0.377 0.375 0.377 0.343 0.402 0.396 0.414 0.396 0.383 0.402 0.396 0.414 0.396 0.383 ns sstl12_m 0.333 0.377 0.375 0.377 0.343 0.561 0.597 0.631 0.597 0.591 0.561 0.597 0.631 0.597 0.591 ns sstl12_s 0.333 0.377 0.375 0.377 0.343 0.789 0.844 0.899 0.844 0.835 0.789 0.844 0.899 0.844 0.835 ns sstl135_dci_f 0.341 0.351 0.384 0.351 0.367 0.426 0.420 0.439 0.422 0.414 0.426 0.420 0.439 0.422 0.414 ns sstl135_dci_m 0.341 0.351 0.384 0.351 0.367 0.586 0.630 0.666 0.630 0.626 0.586 0.630 0.666 0.630 0.626 ns sstl135_dci_s 0.341 0.351 0.384 0.351 0.367 0.814 0.902 0.966 0.895 0.896 0.814 0.902 0.966 0.895 0.896 ns sstl135_f 0.331 0.352 0.373 0.352 0.356 0.397 0.392 0.412 0.394 0.385 0.397 0.392 0.412 0.394 0.385 ns table 28: iob high performance (hp) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 29 table 29 specifies the values of t outbuf_delay_te_pad and t inbuf_delay_ibufdis_o . t outbuf_delay_te_pad is the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). t inbuf_delay_ibufdis_o is the iob delay from ibufdisable to o output. in hp i/o banks, the internal dci termination tu rn-off time is always faster than t outbuf_delay_te_pad when the dcitermdisable pin is used. in hd i/o banks, the in ternal in_term termination turn-off time is always faster than t outbuf_delay_te_pad when the intermdisable pin is used. sstl135_m 0.331 0.352 0.373 0.352 0.356 0.565 0.599 0.633 0.598 0.593 0.565 0.599 0.633 0.598 0.593 ns sstl135_s 0.331 0.352 0.373 0.352 0.356 0.789 0.850 0.907 0.849 0.841 0.789 0.850 0.907 0.849 0.841 ns sstl15_dci_f 0.332 0.349 0.362 0.349 0.346 0.424 0.421 0.439 0.423 0.422 0.424 0.421 0.439 0.423 0.422 ns sstl15_dci_m 0.332 0.349 0.362 0.349 0.346 0.591 0.632 0.667 0.632 0.627 0.591 0.632 0.667 0.632 0.627 ns sstl15_dci_s 0.332 0.349 0.362 0.349 0.346 0.816 0.906 0.971 0.906 0.898 0.816 0.906 0.971 0.906 0.898 ns sstl15_f 0.32 0.356 0.385 0.356 0.353 0.393 0.392 0.412 0.392 0.386 0.393 0.392 0.412 0.392 0.386 ns sstl15_m 0.32 0.356 0.385 0.356 0.353 0.564 0.598 0.633 0.598 0.592 0.564 0.598 0.633 0.598 0.592 ns sstl15_s 0.32 0.356 0.385 0.356 0.353 0.790 0.853 0.910 0.85 0.844 0.790 0.853 0.910 0.85 0.844 ns sstl18_i_dci_f 0.333 0.353 0.360 0.353 0.347 0.418 0.425 0.440 0.424 0.416 0.418 0.425 0.440 0.424 0.416 ns sstl18_i_dci_m 0.333 0.353 0.360 0.353 0.347 0.593 0.633 0.670 0.634 0.629 0.593 0.633 0.670 0.634 0.629 ns sstl18_i_dci_s 0.333 0.353 0.360 0.353 0.347 0.821 0.910 0.978 0.911 0.903 0.821 0.910 0.978 0.911 0.903 ns sstl18_i_f 0.323 0.355 0.378 0.355 0.364 0.388 0.395 0.415 0.392 0.387 0.388 0.395 0.415 0.392 0.387 ns sstl18_i_m 0.323 0.355 0.378 0.355 0.364 0.567 0.603 0.638 0.603 0.596 0.567 0.603 0.638 0.603 0.596 ns sstl18_i_s 0.323 0.355 0.378 0.355 0.364 0.794 0.861 0.920 0.860 0.851 0.794 0.861 0.920 0.860 0.851 ns sub_lvds 0.315 0.352 0.406 0.352 0.348 0.387 0.398 0.418 0.398 0.390 0.387 0.398 0.418 0.398 0.390 ns table 29: iob 3-state output switching characteristics symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 t outbuf_delay_te_pad t input to pad high-impedance for hd i/o banks ns t input to pad high-impedance for hp i/o banks ns t inbuf_delay_ibufdis_o ibuf turn-on time from ibufdisable to o output for hd i/o banks ns ibuf turn-on time from ibufdisable to o output for hp i/o banks ns table 28: iob high performance (hp) switching characteristics (cont?d) i/o standards t inbuf_delay_pad_i t outbuf_delay_o_pad t outbuf_delay_td_pad units 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 -3 -2 -1 -2 -1 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 30 i/o standard adjustment measurement methodology input delay measurements table 30 shows the test setup parameters used for measuring input delay. table 30: input delay measurement methodology description i/o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) lvcmos, 1.2v lvcmos12 0.1 1.1 0.6 ? lvcmos, lvdci, hslvdci, 1.5v lvcmos15, lvdci_15, hslvdci_15 0.1 1.4 0.75 ? lvcmos, lvdci, hslvdci, 1.8v lvcmos18, lvdci_18, hslvdci_18 0.1 1.7 0.9 ? lvcmos, 2.5v lvcmos25 0.1 2.4 1.25 ? lvcmos, 3.3v lvcmos33 0.1 3.2 1.65 ? lvttl, 3.3v lvttl 0.1 3.2 1.65 ? hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 v ref ?0.5 v ref +0.5 v ref 0.6 hstl, class i, 1.5v hstl_i v ref ?0.65 v ref +0.65 v ref 0.75 hstl, class i, 1.8v hstl_i_18 v ref ?0.8 v ref +0.8 v ref 0.9 hsul (high-speed unterminated logic), 1.2v hsul_12 v ref ?0.5 v ref +0.5 v ref 0.6 sstl12 (stub series terminated logic), 1.2v sstl12 v ref ?0.5 v ref +0.5 v ref 0.6 sstl135 and sstl135 class ii, 1.35v sstl135, sstl135_ii v ref ?0.575 v ref +0.575 v ref 0.675 sstl15 and sstl15 class ii, 1.5v sstl15, sstl15_ii v ref ?0.65 v ref +0.65 v ref 0.75 sstl18, class i and ii, 1.8v sstl18_i, sstl18_ii v ref ?0.8 v ref +0.8 v ref 0.9 pod10, 1.0v pod10 v ref ?0.6 v ref +0.6 v ref 0.7 pod12, 1.2v pod12 v ref ?0.74 v ref +0.74 v ref 0.84 diff_hstl, class i, 1.2v diff_hstl_i_12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_hstl, class i, 1.5v diff_hstl_i 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_hstl, class i, 1.8v diff_hstl_i_18 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_hsul, 1.2v diff_hsul_12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl, 1.2v diff_sstl12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl135 and diff_sstl135 class ii, 1.35v diff_sstl135, diff_sstl135_ii 0.675 ? 0.125 0.675 + 0.125 0 (6) ? diff_sstl15 and diff_sstl15 class ii, 1.5v diff_sstl15, diff_sstl15_ii 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_sstl18_i, diff_sstl18_ii, 1.8v diff_sstl18_i, diff_sstl18_ii 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_pod10, 1.0v diff_pod10 0.7 ? 0.125 0.7 + 0.125 0 (6) ? diff_pod12, 1.2v diff_pod12 0.84 ? 0.125 0.84 + 0.125 0 (6) ? lvds (low-voltage differential signaling), 1.8v lvds 0.9 ? 0.125 0.9 + 0.125 0 (6) ? s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 31 lvds_25, 2.5v lvds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? sub_lvds, 1.8v sub_lvds 0.9 ? 0.125 0.9 + 0.125 0 (6) ? slvs, 1.8v slvs_400_18 0.9 ? 0.125 0.9 + 0.125 0 (6) ? slvs, 2.5v slvs_400_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? lvpecl, 2.5v lvpecl 1.25 ? 0.125 1.25 + 0.125 0 (6) ? mipi d-phy (high speed) 1.2v mipi_dphy_dci_hs 0.2 ? 0.125 0.2 + 0.125 0 (6) ? mipi d-phy (low power) 1.2v mipi_dphy_dci_lp 0.715 ? 0.2 0.715 + 0.2 0 (6) ? notes: 1. the input delay measurement methodology parameters for lvdci/hslvdci ar e the same for lvcmos standards of the same voltage. parameters for all other dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage referenc e that bears no relation to the v ref /v meas parameters found in ibis models and/or noted in figure 1 . 6. the value given is the differential input voltage. table 30: input delay measurement methodology (cont?d) description i/o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 32 output delay measurements output delays are measured with short output traces . standard termination was used for all testing. the propagation delay of the trace is characterized separa tely and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 1 and figure 2 . parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagat ion delay in any given application can be obtained through ibis simulation, using this method: 1. simulate the output driver of choice into the generalized test setup using values from table 31 . 2. record the time to v meas . 3. simulate the output driver of choice into the ac tual pcb trace and load using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of step 2 and step 4 . the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 1 figure 1: single-ended test setup x-ref target - figure 2 figure 2: differential test setup v ref r ref v meas (voltage level when taking delay measurement) c ref (probe capacitance) output ds922_01_ 080415 r ref v meas + ? c ref output ds922_02_ 080415 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 33 table 31: output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 1.2v lvcmos12 1m 0 0.6 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 3.3v lvcmos33 1m 0 1.65 0 lvttl, 3.3v lvttl 1m 0 1.65 0 lvdci, hslvdci, 1.5v lvdci_15, hslvdci_15 50 0 v ref 0.75 lvdci, hslvdci, 1.8v lvdci_15, hslvdci_18 50 0 v ref 0.9 hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 50 0 v ref 0.6 hstl, class i, 1.5v hstl_i 50 0 v ref 0.75 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hsul (high-speed unterminated logic), 1.2v hsul_12 50 0 v ref 0.6 sstl12 (stub series terminated logic), 1.2v sstl12 50 0 v ref 0.6 sstl135 and sstl135 class ii, 1.35v sstl135, sstl135_ii 50 0 v ref 0.675 sstl15 and sstl15 class ii, 1.5v sstl15, sstl15_ii 50 0 v ref 0.75 sstl18, class i and class ii, 1.8v sstl18_i, sstl18_ii 50 0 v ref 0.9 pod10, 1.0v pod10 50 0 v ref 1.0 pod12, 1.2v pod12 50 0 v ref 1.2 diff_hstl, class i, 1.2v diff_hstl_i_12 50 0 v ref 0.6 diff_hstl, class i, 1.5v diff_hstl_i 50 0 v ref 0.75 diff_hstl, class i, 1.8v diff_hstl_i_18 50 0 v ref 0.9 diff_hsul, 1.2v diff_hsul_12 50 0 v ref 0.6 diff_sstl12, 1.2v diff_sstl12 50 0 v ref 0.6 diff_sstl135 and diff_sstl135 class ii, 1.35v diff_sstl135, diff_sstl135_ii 50 0 v ref 0.675 diff_sstl15 and diff_sstl15 class ii, 1.5v diff_sstl15, diff_sstl15_ii 50 0 v ref 0.75 diff_sstl18, class i and ii, 1.8v diff_sstl18_i, diff_sstl18_ii 50 0 v ref 0.9 diff_pod10, 1.0v diff_pod10 50 0 v ref 1.0 diff_pod12, 1.2v diff_pod12 50 0 v ref 1.2 lvds (low-voltage differential signaling), 1.8v lvds 100 0 0 (2) 0 sub_lvds, 1.8v sub_lvds 100 0 0 (2) 0 mipi d-phy (high speed) 1.2v mipi_dphy_dci_hs 100 0 0 (2) 0 mipi d-phy (low power) 1.2v mipi_dphy_dci_lp 1m 0 0.6 0 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 34 block ram and fifo switching characteristics table 32: block ram and fifo switching characteristics symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 maximum frequency f max_wf_nc block ram (write_first and no_change modes). 825 737 645 585 516 mhz f max_rf block ram (read_first mode). 718 637 575 510 460 mhz f max_fifo fifo in all modes without ecc. 825 737 645 585 516 mhz f max_ecc block ram and fifo in ecc configuration without pipeline. 718 637 575 510 460 mhz block ram and fifo in ecc configuration with pipeline and block ram in write_first or no_change mode. 825 737 645 585 516 mhz t pw (1) minimum pulse width. 495 542 543 577 578 ps block ram and fifo clock-to-out delays t rcko_do clock clk to dout output (without output register). 0.92 1.03 1.11 1.46 1.54 ns, max t rcko_do_reg clock clk to dout output (with output register). 0.27 0.29 0.31 0.42 0.44 ns, max notes: 1. the mmcm and pll duty_cycle attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 35 ultraram switching characteristics the ultrascale architecture and product overview ( ds890 ) lists the kintex ultrascale+ fpgas that include this memory. input/output delay switching characteristics table 33: ultraram switching characteristics symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 maximum frequency f max ultraram maximum frequency with oreg_b. 650 600 600 500 500 mhz f max_ecc ultraram maximum frequency without oreg_b and en_ecc_rd_b = true. 450 400 400 325 325 mhz f max_norpipeline ultraram maximum frequency with oreg_b = false and en_ecc_rd_b = false. 550 500 500 425 425 mhz t pw (1) minimum pulse width. 650 700 700 800 800 ps t rstpw asynchronous reset minimum pulse width. 550 600 600 650 650 ps notes: 1. the mmcm and pll duty_cycle attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies. table 34: input/output delay switching characteristics symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 f refclk refclk frequency (component mode). 200 to 800 mhz refclk frequency (native mode). 200 to 2400 200 to 2400 200 to 2133 mhz t minper_rst minimum reset pulse width. 52.00 ns t idelay_resolution / t odelay_resolution idelay/odelay chain resolution. 2.5 to 15 ps s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 36 dsp48 slice switching characteristics clock buffers and networks table 35: dsp48 slice switching characteristics symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 maximum frequency f max with all registers used. 891 775 645 644 600 mhz f max_patdet with pattern detector. 794 687 571 562 524 mhz f max_mult_nomreg two register multiply without mreg. 635 544 456 440 413 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect. 577 492 410 395 371 mhz f max_preadd_noadreg without adreg. 655 565 468 453 423 mhz f max_nopipelinereg without pipeline registers (mreg, adreg). 483 410 338 323 304 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect. 448 379 314 299 280 mhz table 36: clock buffers switching characteristics symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 global clock switching characte ristics (including bufgctrl) f max maximum frequency of a global clock tree (bufg). 891 775 667 725 667 mhz global clock buffer with input divide capability (bufgce_div) f max maximum frequency of a global clock buffer with input divide capability (bufgce_div). 891 775 667 725 667 mhz global clock buffer with clock enable (bufgce) f max maximum frequency of a global clock buffer with clock enable (bufgce). 891 775 667 725 667 mhz leaf clock buffer with clock enable (bufce_leaf) f max maximum frequency of a leaf clock buffer with clock enable (bufce_leaf). 891 775 667 725 667 mhz gth or gty clock buffer with clock enable and clock input divide capability (bufg_gt) f max maximum frequency of a serial transceiver clock buffer with clock enable and clock input divide capability. 512 512 512 512 512 mhz s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 37 mmcm switching characteristics table 37: mmcm specification symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 mmcm_f inmax maximum input clock frequency. 1066 933 800 933 800 mhz mmcm_f inmin minimum input clock frequency. 10 10 10 10 10 mhz mmcm_f injitter maximum input clock period jitter. < 20 % of clock input period or 1 ns max mmcm_f induty input duty cycle range: 10?49 mhz. 25?75 % input duty cycle range: 50?199 mhz. 30?70 % input duty cycle range: 200?399 mhz. 35?65 % input duty cycle range: 400?499 mhz. 40?60 % input duty cycle range: >500 mhz. 45?55 % mmcm_f min_psclk minimum dynamic phase shift clock frequency. 0.01 0.01 0.01 0.01 0.01 mhz mmcm_f max_psclk maximum dynamic phase shift clock frequency. 550 500 450 500 450 mhz mmcm_f vcomin minimum mmcm vco frequency. 800 800 800 800 800 mhz mmcm_f vcomax maximum mmcm vco frequency. 1600 1600 1600 1600 1600 mhz mmcm_f bandwidth low mmcm bandwidth at typical. (1) 1.00 1.00 1.00 1.00 1.00 mhz high mmcm bandwidth at typical. (1) 4.00 4.00 4.00 4.00 4.00 mhz mmcm_t statphaoffset static phase offset of the mmcm outputs. (2) 0.12 0.12 0.12 0.12 0.12 ns mmcm_t outjitter mmcm output jitter. note 3 mmcm_t outduty mmcm output clock duty cycle precision. (4) 0.165 0.20 0.20 0.20 0.20 ns mmcm_t lockmax mmcm maximum lock time for mmcm_f pfdmin . 100 100 100 100 100 s mmcm_f outmax mmcm maximum output frequency. 891 775 667 725 667 mhz mmcm_f outmin mmcm minimum output frequency. (4)(5) 6.25 6.25 6.25 6.25 6.25 mhz mmcm_t extfdvar external clock feedback variation. < 20 % of clock input period or 1 ns max mmcm_rst minpulse minimum reset pulse width. 5.00 5.00 5.00 5.00 5.00 ns mmcm_f pfdmax maximum frequency at the phase frequency detector. 550 500 450 500 450 mhz mmcm_f pfdmin minimum frequency at the phase frequency detector. 10 10 10 10 10 mhz mmcm_t fbdelay maximum delay in the feedback path. 5 ns max or one clock cycle notes: 1. the mmcm does not filter typical spread-spectrum input cloc ks because they are usually far below the bandwidth filter frequencies. 2. the static offset is measured between any mmcm outputs with identical phase. 3. values for this parameter are av ailable in the clocking wizard. 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 38 pll switching characteristics table 38: pll specification (1) symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 pll_f inmax maximum input clock frequency. 1066 933 800 933 800 mhz pll_f inmin minimum input clock frequency. 70 70 70 70 70 mhz pll_f injitter maximum input clock period jitter. < 20% of clock input period or 1 ns max pll_f induty input duty cycle range: 70?399 mhz. 35?65 % input duty cycle range: 400?499 mhz. 40?60 % input duty cycle range: >500 mhz. 45?55 % pll_f vcomin minimum pll vco frequency. 750 750 750 750 750 mhz pll_f vcomax maximum pll vco frequency. 1500 1500 1500 1500 1500 mhz pll_t statphaoffset static phase offset of the pll outputs. (2) 0.12 0.12 0.12 0.12 0.12 ns pll_t outjitter pll output jitter. note 3 pll_t outduty pll clkout0, clkout0b, clkout1, clkout1b duty-cycle precision. (4) 0.165 0.20 0.20 0.20 0.20 ns pll_t lockmax pll maximum lock time. 100 s pll_f outmax pll maximum output frequency at clkout0, clkout0b, clkout1, clkout1b. 891 775 667 725 667 mhz pll maximum output frequency at clkoutphy. 2667 2667 2400 2400 2133 mhz pll_f outmin pll minimum output frequency at clkout0, clkout0b, clkout1, clkout1b. (5) 5.86 5.86 5.86 5.86 5.86 mhz pll minimum output frequency at clkoutphy. 2 x vco mode: 1500, 1 x vco mode: 750 0.5 x vco mode: 375 mhz pll_rst minpulse minimum reset pulse width. 5.00 5.00 5.00 5.00 5.00 ns pll_f pfdmax maximum frequency at the phase frequency detector. 667.5 667.5 667.5 667.5 667.5 mhz pll_f pfdmin minimum frequency at the phase frequency detector. 70 70 70 70 70 mhz pll_f bandwidth pll bandwidth at typical. 14 14 14 14 14 mhz notes: 1. the pll does not filter typical spread-s pectrum input clocks because they are usua lly far below the loop filter frequencies. 2. the static offset is measured betwee n any pll outputs with identical phase. 3. values for this parameter are av ailable in the clocking wizard. 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 39 device pin-to-pin output parameter guidelines the pin-to-pin numbers in table 39 through table 41 are based on the clock root placement in the center of the device. the actual pin-to-pin values will vary if the root placement selected is different. consult the vivado design suite timing report for the actual pin-to-pin values. table 39: global clock input to output dela y without mmcm (near clock region) symbol description device speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 sstl15 global clock input to output delay using output flip-flop, fast slew rate, without mmcm. t ickof global clock input and output flip-flop without mmcm (near clock region). xcku3p 4.59 4.96 5.37 5.72 6.08 ns xcku5p 4.59 4.96 5.37 5.72 6.08 ns xcku9p 5.42 5.76 6.16 7.10 7.16 ns XCKU11P 5.93 6.43 6.87 7.47 7.96 ns xcku13p 5.49 6.05 6.57 7.28 7.82 ns xcku15p 6.27 6.77 7.22 7.94 8.42 ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net. table 40: global clock input to output dela y without mmcm (far clock region) symbol description device speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 sstl15 global clock input to output delay using output flip-flop, fast slew rate, without mmcm. t ickof_far global clock input and output flip-flop without mmcm (far clock region). xcku3p 4.76 5.18 5.61 5.97 6.39 ns xcku5p 4.76 5.18 5.61 5.97 6.39 ns xcku9p 5.62 5.98 6.38 7.39 7.46 ns XCKU11P 6.28 6.79 7.24 7.97 8.45 ns xcku13p 5.69 6.30 6.83 7.60 8.17 ns xcku15p 6.79 7.31 7.79 8.68 9.16 ns notes: 1. this table lists representative values where one global clock in put drives one vertical clock line in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 40 table 41: global clock input to output delay with mmcm symbol description device speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 sstl15 global clock input to ou tput delay using output flip-flo p, fast slew rate, with mmcm. t ickofmmcmcc global clock input and output flip-flop with mmcm. xcku3p 2.33 2.44 2.62 2.84 2.89 ns xcku5p 2.33 2.44 2.62 2.84 2.89 ns xcku9p 2.75 2.82 3.01 3.49 3.43 ns XCKU11P 2.64 2.80 3.04 3.23 3.39 ns xcku13p 2.77 2.82 3.08 3.43 3.53 ns xcku15p 2.78 2.99 3.25 3.39 3.64 ns notes: 1. this table lists representative values where one global clock in put drives one vertical clock li ne in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. 2. mmcm output jitter is already included in the timing calculation. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 41 device pin-to-pin input parameter guidelines the pin-to-pin numbers in table 42 and table 43 are based on the clock root placement in the center of the device. the actual pin-to-pin va lues will vary if the root placemen t selected is different. consult the vivado design suite timing report for the actual pin-to-pin values. table 42: global clock input setup and hold with 3.3v hd i/o without mmcm symbol description device speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 input setup and hold time relative to global clock input signal using sstl15 standard. (1)(2)(3) t psfd_ku3p global clock input and input flip-flop (or latch) without mmcm. setup xcku3p ?0.69 ?0.69 ?0.69 ?0.85 ?0.85 ns t phfd_ku3p hold 1.88 2.09 2.20 2.60 2.82 ns t psfd_ku5p setup xcku5p ?0.69 ?0.69 ?0.69 ?0.85 ?0.85 ns t phfd_ku5p hold 1.88 2.09 2.20 2.60 2.82 ns t psfd_ku9p setup xcku9p ?1.06 ?1.06 ?1.06 ?1.06 ?1.06 ns t phfd_ku9p hold 2.40 2.59 2.71 3.47 3.54 ns t psfd_ku11p setup XCKU11P ?0.72 ?0.72 ?0.72 ?0.89 ?0.89 ns t phfd_ku11p hold 1.91 2.14 2.25 2.64 2.88 ns t psfd_ku13p setup xcku13p ?1.07 ?1.07 ?1.07 ?1.24 ?1.24 ns t phfd_ku13p hold 2.39 2.74 2.94 3.53 3.91 ns t psfd_ku15p setup xcku15p ?0.79 ?0.79 ?0.79 ?0.98 ?0.98 ns t phfd_ku15p hold 2.08 2.31 2.43 2.87 3.11 ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. hold time is measured relative to the glob al clock input signal using the fastest proces s, fastest temperature, and fastest voltage. 2. this table lists representative values where one global clock in put drives one vertical clock lin e in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. 3. use ibis to determine any duty-cycle di stortion incurred using various standards. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 42 table 43: global clock input setup and hold with mmcm symbol description device speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 input setup and hold time relative to global clock input signal using sstl15 standard. (1)(2)(3) t psmmcmcc_ku3p global clock input and input flip-flop (or latch) with mmcm. setup xcku3p 2.24 2.49 2.66 2.69 2.69 ns t phmmcmcc_ku3p hold 0.23 0.23 0.23 0.32 0.39 ns t psmmcmcc_ku5p setup xcku5p 2.24 2.49 2.66 2.69 2.69 ns t phmmcmcc_ku5p hold 0.23 0.23 0.23 0.32 0.39 ns t psmmcmcc_ku9p setup xcku9p 1.88 2.04 2.19 2.19 2.19 ns t phmmcmcc_ku9p hold 0.42 0.42 0.42 0.71 0.71 ns t psmmcmcc_ku11p setup XCKU11P 1.91 2.14 2.33 2.33 2.33 ns t phmmcmcc_ku11p hold 0.25 0.25 0.25 0.37 0.50 ns t psmmcmcc_ku13p setup xcku13p 1.88 2.08 2.26 2.29 2.29 ns t phmmcmcc_ku13p hold 0.36 0.36 0.36 0.50 0.64 ns t psmmcmcc_ku15p setup xcku15p 1.88 2.11 2.28 2.28 2.28 ns t phmmcmcc_ku15p hold 0.33 0.31 0.31 0.49 0.58 ns notes: 1. setup and hold times are measured over worst case conditio ns (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, slowest temperat ure, and slowest voltage. hold time is measured relative to the glob al clock input signal using the fastest proces s, fastest temperature, and fastest voltage. 2. this table lists representative values where one global cloc k input drives one vertical clock line in each accessible column, and where all accessible i/o and clb flip-flops are clocked by the global clock net in a single slr. 3. use ibis to determine any duty-cycle di stortion incurred using various standards. table 44: sampling window description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 t samp_bufg (1) ps t samp_native_dpa ps t samp_native_bisc ps notes: 1. this parameter indicates the total sampling error of the ki ntex ultrascale+ fpga ddr input registers, measured across voltage, temperature, and process. the characterization methodology uses the mm cm to capture the ddr input registers? edges of operation. these measurements include: clk0 mmcm jitter, mmcm accuracy (phase offset), and mmcm phase shift resolution. these measurements do not include package or clock tree skew. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 43 package parameter guidelines the parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows. table 45: package skew symbol description device package value units pkgskew package skew xcku3p sfvb784 ps ffva676 ps ffvb676 ps ffvd900 ps xcku5p sfvb784 ps ffva676 ps ffvb676 ps ffvd900 ps xcku9p ffve900 212 ps XCKU11P ffvd900 ps ffva1156 ps ffve1517 ps xcku13p ffve900 ps xcku15p ffva1156 ps ffve1517 ps ffva1760 ps ffve1760 ps notes: 1. these values represent the worst-case skew between any two se lectio resources in the package: shortest delay to longest delay from die pad to ball. 2. package delay information is available for these device/package combinations. this information can be used to deskew the package. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 44 gth transceiver specifications the ultrascale architecture and product overview ( ds890 ) lists the kintex ultrascale+ fpgas that include the gth transceivers. gth transceiver dc input and output levels table 46 summarizes the dc specifications of the gth transceivers in the kintex ultrascale+ fpgas. consult the ultrascale architecture gt h transceiver user guide ( ug576 ) for further details. table 46: gth transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage (external ac coupled) >10.3125 gb/s ? mv 6.6 gb/s to 10.3125 gb/s ? mv 6.6 gb/s ? mv v in single-ended input voltage. voltage measured at the pin referenced to gnd. dc coupled v mgtavtt =1.2v ?v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt =1.2v ?2/3v mgtavtt ?mv d vppout differential peak-to-peak output voltage (1) transmitter output swing is set to 1010 ??mv v cmoutdc common mode output voltage: dc coupled (equation based) when remote rx is terminated to gnd v mgtavtt /2 ? d vppout /4 mv when remote rx termination is floating v mgtavtt ? d vppout /2 mv when remote rx is terminated to v rx_term (2) mv v cmoutac common mode output voltage: ac coupled (equation based) v mgtavtt ? d vppout /2 mv r in differential input resistance ? 100 ? r out differential output resistance ? 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew (all packages) ??10ps c ext recommended external ac coupling capacitor (3) ??nf notes: 1. the output swing and pre-emphas is levels are programmable using the attributes discussed in the ultrascale architecture gth transceiver user guide ( ug576 ), and can result in values lowe r than reported in this table. 2. v rx_term is the remote rx termination voltage. 3. other values can be used as appropriate to conform to specific protocols and standards. v mgtavtt d vppout 4 ---------------------- ? v mgtavtt v rx_term ? 2 ------------------------------------------------------ - ?? ?? ? s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 45 table 47 and table 48 summarize the dc specifications of the gt h transceivers input and output clocks in kintex ultrascale+ fpgas. consult the ultrascale architecture gth transceiver user guide ( ug576 ) for further details. x-ref target - figure 3 figure 3: single-ended peak-to-peak voltage x-ref target - figure 4 figure 4: differential peak-to-peak voltage table 47: gth transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 250 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 10 ? nf table 48: gth transceiver clock outp ut level specification symbol description conditions min typ max units v ol output high voltage for p and n r t = 100 across p and n signals ? ? mv v oh output low voltage for p and n r t = 100 across p and n signals ? ? mv v ddout d if fe rential outp ut voltage ( p ? n ) , p = h i g h (n?p), n = high r t = 100 across p and n signals ? ? mv v cmout common mode voltage r t = 100 across p and n signals ? ? mv 0 +v p n ds922_03_ 080415 single-ended peak-to-peak voltage 0 +v ?v p?n ds922_04_ 080415 differential peak-to-peak voltage differential peak-to-peak voltage = (single-ended peak-to-peak voltage) x 2 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 46 gth transceiver switching characteristics consult the ultrascale architecture gt h transceiver user guide ( ug576 ) for further information. table 49: gth transceiver performance symbol description output divider speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 f gthmax gth maximum line rate. 16.375 16.375 12.5 12.5 10.3125 gb/s f gthmin gth minimum line rate. 0.50.50.50.50.5gb/s min max min max min max min max min max f gthcrange cpll line rate range (1) . 1 4 12.5 4 12.5 4 8.5 4 8.5 4 8.5 gb/s 2 26.2526.2524.2524.2524.25gb/s 4 1 3.125 1 3.125 1 2.125 1 2.125 1 2.125 gb/s 8 0.5 1.5625 0.5 1.5625 0.5 1.0625 0.5 1.0625 0.5 1.0625 gb/s 16 n/a gb/s min max min max min max min max min max f gthqrange1 qpll0 line rate range (2) . 1 9.8 16.375 9.8 16.375 9.8 12.5 9.8 12.5 9.8 10.3125 gb/s 2 4.9 8.1875 4.9 8.1875 4.9 8.15 4.9 8.1875 4.9 8.15 gb/s 42.45 4.09375 2.45 4.09375 2.45 4.075 2.45 4.09375 2.45 4.075 gb/s 8 1.225 2.04688 1.225 2.04688 1.225 2.0375 1.225 2.04688 1.225 2.0375 gb/s 16 0.6125 1.02344 0.6125 1.02344 0.6125 1.01875 0.6125 1.02344 0.6125 1.01875 gb/s min max min max min max min max min max f gthqrange2 qpll1 line rate range (3) . 1 8.0 13 8.0 13 8.0 12.5 8.0 12.5 8.0 10.3125 gb/s 2 4.06.54.06.54.06.54.06.54.06.5gb/s 4 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 gb/s 8 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 gb/s 16 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 gb/s min max min max min max min max min max f cpllrange cpll frequency range. 26.2526.2524.2524.2524.25ghz f qpll0range qpll0 frequency range. 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 ghz f qpll1range qpll1 frequency range. 813813813813813ghz notes: 1. the values listed are the rounded results of the calculated equation (2 x cpll_frequency)/output_divider. 2. the values listed are the rounded results of the ca lculated equation (qpll0_frequency)/output_divider. 3. the values listed are the rounded results of the ca lculated equation (qpll1_frequency)/output_divider. table 50: gth transceiver dynamic reconfiguration port (drp) switching characteristics symbol description all speed grades units f gthdrpclk gthdrpclk maximum frequency. mhz s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 47 table 51: gth transceiver reference cloc k switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range. 60 ? 820 mhz t rclk reference clock rise time. 20% ? 80% ? 200 ? ps t fclk reference clock fall time. 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle. transceiver pll only 40 50 60 % x-ref target - figure 5 figure 5: reference clock timing parameters table 52: gth transceiver reference clock os cillator selection phase noise mask symbol description offset frequency min typ max units qpll refclkmask (1)(2) qpll0/qpll1 reference clock select phase noise mask at refclk frequency = 312.5 mhz. 10 khz ? ? ?105 dbc/hz 100 khz ? ? ?124 1 mhz ? ? ?130 cpll refclkmask (1)(2) cpll reference clock select phase noise mask at refclk frequency = 312.5 mhz. 10 khz ? ? ?105 dbc/hz 100 khz ? ? ?124 1 mhz ? ? ?130 50 mhz ? ? ?140 notes: 1. for reference clock frequencies other than 312.5 mhz, adjust the phase-noise ma sk values by 20 x log(n/312.5) where n is the new reference clock frequency in mhz. 2. this reference clock phase-noise mask is superseded by an y reference clock phase-noise mask that is specified in a supported protocol, e.g., pcie. table 53: gth transceiver pll/lock time adaptation symbol description conditions all speed grades units min typ max t lock initial pll lock. ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time for decision feedback equalizer (dfe). after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ?ui clock recovery phase acquisition and adaptation time for low-power mode (lpm) when the dfe is disabled. ?ui ds922_05_ 080415 80% 20% t fclk t rclk s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 48 table 54: gth transceiver user clock switching characteristics (1) symbol description data width conditions (bit) speed grade, temper ature ranges, and v ccint operating voltages units 0.90v 0.85v 0.72v internal logic interconnect logic -3 (2) -2 (2)(3) -1 (4) -2 (3) -1 (3)(5) f txoutpma txoutclk maximum frequency sourced from outclkpma 511.719 511.719 390.625 390.625 322.266 mhz f rxoutpma rxoutclk maximum frequency sourced from outclkpma 511.719 511.719 390.625 390.625 322.266 mhz f txoutprogdiv txoutclk maximum frequency sourced from txprogdivclk 511.719 511.719 511.719 511.719 511.719 mhz f rxoutprogdiv rxoutclk maximum frequency sourced from rxprogdivclk 511.719 511.719 511.719 511.719 511.719 mhz f txin txusrclk maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 322.266 mhz 32 32, 64 511.719 511.719 390.625 390.625 322.266 mhz 20 20, 40 409.375 409.375 312.500 312.500 257.813 mhz 40 40, 80 409.375 409.375 312.500 312.500 257.813 mhz f rxin rxusrclk maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 322.266 mhz 32 32, 64 511.719 511.719 390.625 390.625 322.266 mhz 20 20, 40 409.375 409.375 312.500 312.500 257.813 mhz 40 40, 80 409.375 409.375 312.500 312.500 257.813 mhz f txin2 txusrclk2 maximum frequency 16 16 511.719 511.719 390.625 390.625 322.266 mhz 16 32 255.859 255.859 195.313 195.313 161.133 mhz 32 32 511.719 511.719 390.625 390.625 322.266 mhz 32 64 255.859 255.859 195.313 195.313 161.133 mhz 20 20 409.375 409.375 312.500 312.500 257.813 mhz 20 40 204.688 204.688 156.250 156.250 128.906 mhz 40 40 409.375 409.375 312.500 312.500 257.813 mhz 40 80 204.688 204.688 156.250 156.250 128.906 mhz f rxin2 rxusrclk2 maximum frequency 16 16 511.719 511.719 390.625 390.625 322.266 mhz 16 32 255.859 255.859 195.313 195.313 161.133 mhz 32 32 511.719 511.719 390.625 390.625 322.266 mhz 32 64 255.859 255.859 195.313 195.313 161.133 mhz 20 20 409.375 409.375 312.500 312.500 257.813 mhz 20 40 204.688 204.688 156.250 156.250 128.906 mhz 40 40 409.375 409.375 312.500 312.500 257.813 mhz 40 80 204.688 204.688 156.250 156.250 128.906 mhz notes: 1. clocking must be implemented as described in ultrascale architecture gt h transceiver user guide ( ug576 ). 2. for speed grades -3e and -2i, a 16-bit and 20-bit internal da ta path can only be used for line rates less than 8.1875 gb/s. 3. for speed grade -2le, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 gb/s when v ccint = 0.85v or 6.25 gb/s when v ccint = 0.72v. 4. for speed grades -1e and -1i, a 16-bit and 20-bit internal data path can only be used for li ne rates less than 6.25 gb/s. 5. for speed grade -1li, a 16-bit and 20-bit internal data path can only be used for line ra tes less than 6.25 gb/s when v ccint = 0.85v or 5.15625 gb/s when v ccint = 0.72v. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 49 table 55: gth transceiver transmitter switching characteristics symbol description condition min typ max units f gthtx serial data rate range 0.500 ? f gthmax gb/s t rtx tx rise time 20%?80% ? 40 ? ps t ftx tx fall time 80%?20% ? 40 ? ps t llskew tx lane-to-lane skew (1) ?? ps v txoobvdpp electrical idle amplitude ? ? mv t txoobtransition electrical idle transition time ? ? ns t j16.375 total jitter (2)(4) 16.375 gb/s ?? ui d j16.375 deterministic jitter (2)(4) ?? ui t j15.1 total jitter (2)(4) 15.1 gb/s ?? ui d j15.1 deterministic jitter (2)(4) ?? ui t j14.1 total jitter (2)(4) 14.1 gb/s ?? ui d j14.1 deterministic jitter (2)(4) ?? ui t j13.1 total jitter (2)(4) 13.1 gb/s ?? ui d j13.1 deterministic jitter (2)(4) ?? ui t j12.5 total jitter (2)(4) 12.5 gb/s ?? ui d j12.5 deterministic jitter (2)(4) ?? ui t j11.3 total jitter (2)(4) 11.3 gb/s ?? ui d j11.3 deterministic jitter (2)(4) ?? ui t j10.3125_qpll total jitter (2)(4) 10.3125 gb/s ?? ui d j10.3125_qpll deterministic jitter (2)(4) ?? ui t j10.3125_cpll total jitter (3)(4) 10.3125 gb/s ?? ui d j10.3125_cpll deterministic jitter (3)(4) ?? ui t j9.953 total jitter (2)(4) 9.953 gb/s ?? ui d j9.953 deterministic jitter (2)(4) ?? ui t j8.0_qpll total jitter (2)(4) 8.0 gb/s ?? ui d j8.0_qpll deterministic jitter (2)(4) ?? ui t j8.0_cpll total jitter (3)(4) 8.0 gb/s ?? ui d j8.0_cpll deterministic jitter (3)(4) ?? ui t j6.6_cpll total jitter (3)(4) 6.6 gb/s ?? ui d j6.6_cpll deterministic jitter (3)(4) ?? ui t j5.0 total jitter (3)(4) 5.0 gb/s ?? ui d j5.0 deterministic jitter (3)(4) ?? ui t j4.25 total jitter (3)(4) 4.25 gb/s ?? ui d j4.25 deterministic jitter (3)(4) ?? ui t j3.75 total jitter (3)(4) 3.75 gb/s ?? ui d j3.75 deterministic jitter (3)(4) ?? ui t j3.20 total jitter (3)(4) 3.20 gb/s (5) ?? ui d j3.20 deterministic jitter (3)(4) ?? ui t j3.20l total jitter (3)(4) 3.20 gb/s (6) ?? ui d j3.20l deterministic jitter (3)(4) ?? ui s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 50 t j2.5 total jitter (3)(4) 2.5 gb/s (7) ?? ui d j2.5 deterministic jitter (3)(4) ?? ui t j1.25 total jitter (3)(4) 1.25 gb/s (8) ?? ui d j1.25 deterministic jitter (3)(4) ?? ui t j500 total jitter (3)(4) 500 mb/s ?? ui d j500 deterministic jitter (3)(4) ?? ui notes: 1. using same refclk input with tx phas e alignment enabled for up to four consec utive transmitters (one fully populated gth quad) at the maximum line rate. 2. using qpll_fbdiv = 40, 20-bit internal data width. these va lues are not intended for pr otocol specific compliance determinations. 3. using cpll_fbdiv = 2, 20-bit internal da ta width. these values are not intend ed for protocol specific compliance determinations. 4. all jitter values are based on a bit-error ratio of 10 -12 . 5. cpll frequency at 3.2 ghz and txout_div = 2. 6. cpll frequency at 1.6 ghz and txout_div = 1. 7. cpll frequency at 2.5 ghz and txout_div = 2. 8. cpll frequency at 2.5 ghz and txout_div = 4. table 56: gth transceiver receiver switching characteristics symbol description condition min typ max units f gthrx serial data rate 0.500 ? f gthmax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ?10?ns r xoobvdpp oob detect threshold peak-to-peak ? mv r xsst receiver spread-spectrum tracking (1) modulated at 33 khz ? 0 ppm r xrl run length (cid) ? ? ui r xppmtol data/refclk ppm offset tolerance bit rates 6.6 gb/s ? ppm bit rates > 6.6 gb/s and 8.0 gb/s ?ppm bit rates > 8.0 gb/s ? ppm sj jitter tolerance (2) j t_sj16.375 sinusoidal jitter (qpll) (3) 16.375 gb/s ? ? ui j t_sj15.1 sinusoidal jitter (qpll) (3) 15.1 gb/s ? ? ui j t_sj14.1 sinusoidal jitter (qpll) (3) 14.1 gb/s ? ? ui j t_sj13.1 sinusoidal jitter (qpll) (3) 13.1 gb/s ? ? ui j t_sj12.5 sinusoidal jitter (qpll) (3) 12.5 gb/s ? ? ui j t_sj11.3 sinusoidal jitter (qpll) (3) 11.3 gb/s ? ? ui j t_sj10.32_qpll sinusoidal jitter (qpll) (3) 10.32 gb/s ? ? ui j t_sj10.32_cpll sinusoidal jitter (cpll) (3) 10.32 gb/s ? ? ui j t_sj9.953 sinusoidal jitter (qpll) (3) 9.953 gb/s ? ? ui j t_sj8.0_qpll sinusoidal jitter (qpll) (3) 8.0 gb/s ? ? ui j t_sj8.0_cpll sinusoidal jitter (cpll) (3) 8.0 gb/s ? ? ui j t_sj6.6_cpll sinusoidal jitter (cpll) (3) 6.6 gb/s ? ? ui table 55: gth transceiver transmitter switching characteristics (cont?d) symbol description condition min typ max units s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 51 j t_sj5.0 sinusoidal jitter (cpll) (3) 5.0 gb/s ? ? ui j t_sj4.25 sinusoidal jitter (cpll) (3) 4.25 gb/s ? ? ui j t_sj3.75 sinusoidal jitter (cpll) (3) 3.75 gb/s ? ? ui j t_sj3.2 sinusoidal jitter (cpll) (3) 3.2 gb/s (4) ??ui j t_sj3.2l sinusoidal jitter (cpll) (3) 3.2 gb/s (5) j t_sj2.5 sinusoidal jitter (cpll) (3) 2.5 gb/s (6) ??ui j t_sj1.25 sinusoidal jitter (cpll) (3) 1.25 gb/s (7) ??ui j t_sj500 sinusoidal jitter (cpll) (3) 500 mb/s ? ? ui sj jitter tolerance with stressed eye (2) j t_tjse3.2 total jitter with stressed eye (8) 3.2 gb/s ? ? ui j t_tjse6.6 6.6 gb/s ? ? ui j t_sjse3.2 sinusoidal jitter with stressed eye (8) 3.2 gb/s ? ? ui j t_sjse6.6 6.6 gb/s ? ? ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 10 ?12 . 3. the frequency of the injected sinusoidal jitter is 80 mhz. 4. cpll frequency at 3.2 ghz and rxout_div = 2. 5. cpll frequency at 1.6 ghz and rxout_div = 1. 6. cpll frequency at 2.5 ghz and rxout_div = 2. 7. cpll frequency at 2.5 ghz and rxout_div = 4. 8. composite jitter with rx equalizer enabled. dfe disabled. table 56: gth transceiver receiver switching characteristics (cont?d) symbol description condition min typ max units s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 52 gth transceiver electrical compliance the ultrascale architecture gth transceiver user guide ( ug576 ) contains recommend ed use modes that ensure compliance for the protocols listed in table 57 . the transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. table 57: gth transceiver protocol list protocol specification serial rate (gb/s) electrical compliance caui-10 ieee 802.3-2012 10.3125 compliant nppi ieee 802.3-2012 10.3125 compliant 10gbase-kr ieee 802.3-2012 10.3125 compliant sfp+ sff-8431 (sr and lr) 9.95328?11.10 compliant xfp inf-8077i, revision 4.5 10.3125 compliant rxaui cei-6g-sr 6.25 compliant xaui ieee 802.3-2012 3.125 compliant 1000base-x ieee 802.3-2012 1.25 compliant otu2 itu g.8251 10.709225 compliant otu4 (otl4.10) oif-cei-11g-sr 11.180997 compliant oc-3/12/48/192 gr-253-core 0.1555?9.956 compliant interlaken oif-cei-6g, oif-cei-11g-sr 4.25?12.5 compliant pcie gen1, 2, 3 pci express base 3.0 2.5, 5.0, and 8.0 compliant sdi smpte 424m-2006 0.27?2.97 compliant hybrid memory cube (hmc) hmc-15g-sr 10, 12.5, and 15.0 compliant cpri cpri_v_6_1_2014-07-01 0.6144?12.165 compliant passive optical network (pon) 10g-epon, 1g-epon, ng-pon2, xg-pon, and 2.5g-pon 0.155?10.3125 compliant jesd204a/b oif-cei-6g, oif-cei-11g 3.125?12.5 compliant serial rapidio rapidio specification 3.1 1.25?10.3125 compliant displayport (source only) dp 1.2b cts 1.62?5.4 compliant fibre channel fc-pi-4 1.0625?14.025 compliant sata gen1, 2, 3 serial ata revision 3.0 specification 1.5, 3.0, and 6.0 compliant sas gen1, 2, 3 t10/bsr incits 519 3.0, 6.0, and 12.0 compliant sfi-5 oif-sfi5-01.0 0.625?12.5 compliant s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 53 gth transceiver protocol jitter characteristics for table 58 through table 63 , the ultrascale architecture gt h transceiver user guide ( ug576 ) contains recommended settings for optimal usage of protocol specific characteristics. table 58: gigabit ethernet protocol characteristics (gth transceivers) description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 ? ui table 59: xaui protocol characteristics (gth transceivers) description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? ui xaui receiver high frequency jitter tolerance total receiver jitter tolerance 3125 ? ui table 60: pci express protocol characteristics (gth transceivers) (1) standard description condition line rate (mb/s) min max units pci express transmitter jitter generation pci express gen 1 total transmitter jitter 2500 ? ui pci express gen 2 total transmitter jitter 5000 ? ui pci express gen 3 (2) total transmitter jitter uncorrelated 8000 ?ps deterministic transmitter jitter uncorrelated ? ps pci express receiver high frequency jitter tolerance pci express gen 1 total receiver jitter tolerance 2500 ? ui pci express gen 2 (2) receiver inherent timing error 5000 ?ui receiver inherent deterministic timing error ? ui pci express gen 3 (2) receiver sinusoidal jitter tolerance 0.03 mhz?1.0 mhz 8000 ?ui 1.0mhz?10mhz note 3 ?ui 10 mhz?100 mhz ? ui notes: 1. tested per card electrom echanical (cem) methodology. 2. using common refclk. 3. between 1 mhz and 10 mhz the minimum sinusoidal jitter roll-off with a slope of 20 db/decade. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 54 table 61: cei-6g and cei-11g protocol char acteristics (gth transceivers) description line rate (mb/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? ui cei-6g-lr ? ui cei-6g receiver high frequency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr ? ui cei-6g-lr ? ui cei-11g transmitter jitter generation total transmitter jitter (2) 9950?11100 cei-11g-sr ? ui cei-11g-lr/mr ? ui cei-11g receiver high frequency jitter tolerance total receiver jitter tolerance (2) 9950?11100 cei-11g-sr ? ui cei-11g-mr ? ui cei-11g-lr ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. 2. tested at line rate of 9950 mb/s using 155.46875 mhz reference clock and 11100 mb/s using 173.4375 mhz reference clock. table 62: sfp+ protocol characteristics (gth transceivers) description line rate (mb/s) min max units sfp+ transmitter jitter generation total transmitter jitter 9830.40 (1) ?ui 9953.00 10312.50 10518.75 11100.00 sfp+ receiver frequency jitter tolerance total receiver jitter tolerance 9830.40 (1) ?ui 9953.00 10312.50 10518.75 11100.00 notes: 1. line rated used for cpri over sfp+ applications. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 55 table 63: cpri protocol characteri stics (gth transceivers) description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter 614.4 ? ui 1228.8 ? ui 2457.6 ? ui 3072.0 ? ui 4915.2 ? ui 6144.0 ? ui 9830.4 ? note 1 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance 614.4 ? ui 1228.8 ? ui 2457.6 ? ui 3072.0 ? ui 4915.2 ? ui 6144.0 ? ui 9830.4 note 1 ?ui notes: 1. tested per sfp+ specification, see table 62 . s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 56 gty transceiver specifications the ultrascale architecture and product overview ( ds890 ) lists the kintex ultrascale+ fpgas that include the gty transceivers. gty transceiver dc input and output levels table 64 summarizes the dc specifications of the gty tr ansceivers in kintex ultrascale+ fpgas. consult www.xilinx.com/products/tec hnology/high-speed-serial for further details. table 64: gty transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage (external ac coupled) >10.3125 gb/s ? mv 6.6 gb/s to 10.3125 gb/s ? mv 6.6 gb/s ? mv v in single-ended input voltage. voltage measured at the pin referenced to gnd. dc coupled v mgtavtt =1.2v ?v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt =1.2v ?2/3v mgtavtt ?mv d vppout differential peak-to-peak output voltage (1) transmitter output swing is set to 1010 ??mv v cmoutdc common mode output voltage: dc coupled (equation based) when remote rx is terminated to gnd v mgtavtt /2 ? d vppout /4 mv when remote rx termination is floating v mgtavtt ? d vppout /2 mv when remote rx is terminated to v rx_term (2) mv v cmoutac common mode output voltage: ac coupled equation based v mgtavtt ? d vppout /2 mv r in differential input resistance ? 100 ? r out differential output resistance ? 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew ? ? 10 ps c ext recommended external ac coupling capacitor (3) ? 100 ? nf notes: 1. the output swing and pre-emphasis le vels are programmable using the gty transceiver attributes discussed in the ultrascale archit ecture gty transceiver user guide ( ug578 ) and can result in values lowe r than reported in this table. 2. v rx_term is the remote rx termination voltage. 3. other values can be used as appropriate to conform to specific protocols and standards. v mgtavtt d vppout 4 ---------------------- ? v mgtavtt v rx_term ? 2 ------------------------------------------------------ - ?? ?? ? s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 57 table 65 summarizes the dc specifications of the clock in put of the gty transceivers in kintex ultrascale+ fpgas. consult www.xilinx.com/products/te chnology/high-speed-serial for further details. x-ref target - figure 6 figure 6: single-ended peak-to-peak voltage x-ref target - figure 7 figure 7: differential peak-to-peak voltage table 65: gty transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 250 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 10 ? nf table 66: gty transceiver clock output level specification symbol description conditions min typ max units v ol output high voltage for p and n r t = 100 across p and n signals ? ? mv v oh output low voltage for p and n r t = 100 across p and n signals ? ? mv v ddout d if fe rential outp ut voltage ( p ? n ) , p = h i g h (n?p), n = high r t = 100 across p and n signals ? ? mv v cmout common mode voltage r t = 100 across p and n signals ? ? mv 0 +v p n ds922_03_ 080415 single-ended peak-to-peak voltage 0 +v ?v p?n ds922_04_ 080415 differential peak-to-peak voltage differential peak-to-peak voltage = (single-ended peak-to-peak voltage) x 2 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 58 gty transceiver switching characteristics consult www.xilinx.com/products/tec hnology/high-speed-serial for further information. table 67: gty transceiver performance symbol description output divider speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 f gtymax gty maximum line rate 32.75 (1) 28.21 (1) 12.5 28.21 (1) 12.5 gb/s f gtymin gty minimum line rate 0.5 0.5 0.5 0.5 0.5 gb/s min max min max min max min max min max f gtycrange cpll line rate range (2) 1 4.0 12.5 4.0 12.5 4.0 8.5 4.0 12.5 4.0 8.5 gb/s 2 2.0 6.25 2.0 6.25 2.0 4.25 2.0 6.25 2.0 4.25 gb/s 4 1.0 3.125 1.0 3.125 1.0 2.125 1.0 3.125 1.0 2.125 gb/s 8 0.5 1.5625 0.5 1.5625 0.5 1.0625 0.5 1.5625 0.5 1.0625 gb/s 16 n/a gb/s 32 n/a gb/s min max min max min max min max min max f gtyqrange1 qpll0 line rate range (3) 1 19.6 32.75 19.6 28.21 n/a 19.6 28.21 n/a gb/s 1 9.8 16.375 9.8 16.375 9.8 12.5 9.8 16.375 9.8 12.5 gb/s 2 4.9 8.1875 4.9 8.1875 4.9 8.1875 4.9 8.1875 4.9 8.1875 gb/s 4 2.45 4.09375 2.45 4.09375 2.45 4.09375 2.45 4.09375 2.45 4.09375 gb/s 8 1.225 2.04688 1.225 2.04688 1.225 2.04688 1.225 2.04688 1.225 2.04688 gb/s 16 0.6125 1.02344 0.6125 1.02344 0.6125 1.02344 0.6125 1.02344 0.6125 1.02344 gb/s min max min max min max min max min max f gtyqrange2 qpll1 line rate range (4) 1 16.0 26.0 16.0 26.0 n/a 16.0 26.0 n/a gb/s 1 8.0 13.0 8.0 13.0 8.0 12.5 8.0 13.0 8.0 12.5 gb/s 2 4.0 6.5 4.0 6.5 4.0 6.5 4.0 6.5 4.0 6.5 gb/s 4 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 2.0 3.25 gb/s 8 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 1.0 1.625 gb/s 16 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 0.5 0.8125 gb/s min max min max min max min max min max f cpllrange cpll frequency range 2.0 6.25 2.0 6.25 2.0 4.25 2.0 6.25 2.0 4.25 ghz f qpll0range qpll0 frequency range 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 9.8 16.375 ghz f qpll1range qpll1 frequency range 8.0 13.0 8.0 13.0 8.0 13.0 8.0 13.0 8.0 13.0 ghz notes: 1. gty transceiver line rates are package limited: sfvb784 to 12.5 gb/s; ffva676, ffvd900, and ffva1156 to 16.3 gb/s. 2. the values listed are the rounded results of the calculated equation (2 x cpll_frequency)/output_divider. 3. the values listed are the rounded results of the calc ulated equation (2 x qpll0_frequency)/output_divider. 4. the values listed are the rounded results of the calc ulated equation (2 x qpll1_frequency)/output_divider. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 59 table 68: gty transceiver dynamic reconfiguration port (drp) switching characteristics symbol description all speed grades units f gtydrpclk gtydrpclk maximum frequency. mhz table 69: gty transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range. 60 ? 820 mhz t rclk reference clock rise time. 20% ? 80% ? 200 ? ps t fclk reference clock fall time. 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle. transceiver pll only 40 50 60 % x-ref target - figure 8 figure 8: reference clock timing parameters ds922_05_ 080415 80% 20% t fclk t rclk s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 60 table 70: gty transceiver reference clock os cillator selection phase noise mask (1) symbol description offset frequency min typ max units qpll refclkmask qpll0/qpll1 reference clock select phase noise mask at refclk frequency = 156.25 mhz. 10 khz ? ? ?112 dbc/hz 100 khz ? ? ?128 1 mhz ? ? ?145 qpll0/qpll1 reference clock select phase noise mask at refclk frequency = 312.5 mhz. 10 khz ? ? ?103 dbc/hz 100 khz ? ? ?123 1 mhz ? ? ?143 qpll0/qpll1 reference clock select phase noise mask at refclk frequency =625 mhz. 10 khz ? ? ?98 dbc/hz 100 khz ? ? ?117 1 mhz ? ? ?140 cpll refclkmask cpll reference clock select phase noise mask at refclk frequency = 156.25 mhz. 10 khz ? ? ?112 dbc/hz 100 khz ? ? ?128 1 mhz ? ? ?145 50 mhz ? ? ?145 cpll reference clock select phase noise mask at refclk frequency = 312.5 mhz. 10 khz ? ? ?103 dbc/hz 100 khz ? ? ?123 1 mhz ? ? ?143 50 mhz ? ? ?145 cpll reference clock select phase noise mask at refclk frequency = 625 mhz. 10 khz ? ? ?98 dbc/hz 100 khz ? ? ?117 1 mhz ? ? ?140 50 mhz ? ? ?144 notes: 1. for reference clock frequencies not in this table, use th e phase-noise mask for the nearest reference clock frequency. table 71: gty transceiver pll/lock time adaptation symbol description conditions all speed grades units min typ max t lock initial pll lock. ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time for decision feedback equalizer (dfe). after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ?ui clock recovery phase acquisition and adaptation time for low-power mode (lpm) when the dfe is disabled. ?ui s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 61 table 72: gty transceiver user clock switching characteristics (1) symbol description data width conditions (bit) speed grade and v ccint operating voltages units 0.90v 0.85 0.72 internal logic interconnect logic -3 -2 -1 -2 -1 f txoutpma txoutclk maximum frequency sourced from outclkpma 511.719 511.719 390.625 511.719 322.266 mhz f rxoutpma rxoutclk maximum frequency sourced from outclkpma 511.719 511.719 390.625 511.719 322.266 mhz f txoutprogdiv txoutclk maximum frequency sourced from txprogdivclk 511.719 511.719 511.719 511.719 511.719 mhz f rxoutprogdiv rxoutclk maximum frequency sourced from rxprogdivclk 511.719 511.719 511.719 511.719 511.719 mhz f txin txusrclk maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 322.266 mhz 32 32, 64 511.719 511.719 390.625 390.625 322.266 mhz 64 64, 128 511.719 440.781 195.313 402.813 195.313 mhz 20 20, 40 409.375 409.375 312.500 312.500 312.500 mhz 40 40, 80 409.375 409.375 312.500 350.000 257.813 mhz 80 80, 160 409.375 352.625 156.250 352.625 156.250 mhz f rxin rxusrclk maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 322.266 mhz 32 32, 64 511.719 511.719 390.625 390.625 322.266 mhz 64 64, 128 511.719 440.781 195.313 402.813 195.313 mhz 20 20, 40 409.375 409.375 312.500 312.500 312.500 mhz 40 40, 80 409.375 409.375 312.500 350.000 257.813 mhz 80 80, 160 409.375 352.625 156.250 352.625 156.250 mhz f txin2 txusrclk2 maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 322.266 mhz 32 32, 64 511.719 511.719 390.625 390.625 322.266 mhz 64 64, 128 511.719 440.781 195.313 402.813 195.313 mhz 20 20, 40 409.375 409.375 312.500 312.500 312.500 mhz 40 40, 80 409.375 409.375 312.500 350.000 257.813 mhz 80 80, 160 409.375 352.625 156.250 352.625 156.250 mhz f rxin2 rxusrclk2 maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 322.266 mhz 32 32, 64 511.719 511.719 390.625 390.625 322.266 mhz 64 64, 128 511.719 440.781 195.313 402.813 195.313 mhz 20 20, 40 409.375 409.375 312.500 312.500 312.500 mhz 40 40, 80 409.375 409.375 312.500 350.000 257.813 mhz 80 80, 160 409.375 352.625 156.250 352.625 156.250 mhz notes: 1. clocking must be implem ented as described in the ultrascale architecture gt y transceiver user guide ( ug578 ). s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 62 table 73: gty transceiver transmitter switching characteristics symbol description condition min typ max units f gtytx serial data rate range 0.500 ? f gtymax gb/s t rtx tx rise time 20%?80% ? ? ps t ftx tx fall time 80%?20% ? ? ps t llskew tx lane-to-lane skew (1) ?? ps v txoobvdpp electrical idle amplitude ? ? mv t txoobtransition electrical idle transition time ? ? ns t j32.75 total jitter (2)(4) 32.75 gb/s ?? ui d j32.75 deterministic jitter (2)(4) ?? ui t j16.375 total jitter (2)(4) 16.375 gb/s ?? ui d j16.375 deterministic jitter (2)(4) ?? ui t j12.5 total jitter (2)(4) 12.5 gb/s ?? ui d j12.5 deterministic jitter (2)(4) ?? ui t j11.3 total jitter (2)(4) 11.3 gb/s ?? ui d j11.3 deterministic jitter (2)(4) ?? ui t j10.3125_qpll total jitter (2)(4) 10.3125 gb/s ?? ui d j10.3125_qpll deterministic jitter (2)(4) ?? ui t j10.3125_cpll total jitter (3)(4) 10.3125 gb/s ?? ui d j10.3125_cpll deterministic jitter (3)(4) ?? ui t j9.953 total jitter (2)(4) 9.953 gb/s ?? ui d j9.953 deterministic jitter (2)(4) ?? ui t j9.8 total jitter (2)(4) 9.8 gb/s ?? ui d j9.8 deterministic jitter (2)(4) ?? ui t j8.0_qpll total jitter (2)(4) 8.0 gb/s ?? ui d j8.0_qpll deterministic jitter (2)(4) ?? ui t j8.0_cpll total jitter (3)(4) 8.0 gb/s ?? ui d j8.0_cpll deterministic jitter (3)(4) ?? ui t j6.6_cpll total jitter (3)(4) 6.6 gb/s ?? ui d j6.6_cpll deterministic jitter (3)(4) ?? ui t j5.0 total jitter (3)(4) 5.0 gb/s ?? ui d j5.0 deterministic jitter (3)(4) ?? ui t j4.25 total jitter (3)(4) 4.25 gb/s ?? ui d j4.25 deterministic jitter (3)(4) ?? ui t j3.75 total jitter (3)(4) 3.75 gb/s ?? ui d j3.75 deterministic jitter (3)(4) ?? ui t j3.20 total jitter (3)(4) 3.20 gb/s (5) ?? ui d j3.20 deterministic jitter (3)(4) ?? ui t j3.20l total jitter (3)(4) 3.20 gb/s (6) ?? ui d j3.20l deterministic jitter (3)(4) ?? ui t j2.5 total jitter (3)(4) 2.5 gb/s (7) ?? ui d j2.5 deterministic jitter (3)(4) ?? ui s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 63 t j1.25 total jitter (3)(4) 1.25 gb/s (8) ?? ui d j1.25 deterministic jitter (3)(4) ?? ui t j500 total jitter (3)(4) 500 mb/s ?? ui d j500 deterministic jitter (3)(4) ?? ui notes: 1. using same refclk input with tx phas e alignment enabled for up to four consec utive transmitters (one fully populated gty quad) at maximum line rate. 2. using qpll_fbdiv = 40, 20-bit internal data width. these va lues are not intended for pr otocol specific compliance determinations. 3. using cpll_fbdiv = 2, 20-bit internal da ta width. these values are not intend ed for protocol specific compliance determinations. 4. all jitter values are based on a bit-error ratio of 10 -12 . 5. cpll frequency at 3.2 ghz and txout_div = 2. 6. cpll frequency at 1.6 ghz and txout_div = 1. 7. cpll frequency at 2.5 ghz and txout_div = 2. 8. cpll frequency at 2.5 ghz and txout_div = 4. table 73: gty transceiver transmitter switching characteristics (cont?d) symbol description condition min typ max units s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 64 table 74: gty transceiver receiver switching characteristics symbol description condition min typ max units f gtyrx serial data rate 0.500 ? f gtymax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ??ns r xoobvdpp oob detect threshold peak-to-peak ? mv r xsst receiver spread-spectrum tracking (1) modulated at 33 khz ? ppm r xrl run length (cid) ? ? ui r xppmtol data/refclk ppm offset tolerance bit rates 6.6 gb/s ? ppm bit rates > 6.6 gb/s and 8.0 gb/s ?ppm bit rates > 8.0 gb/s ? ppm sj jitter tolerance (2) j t_sj32.75 sinusoidal jitter (qpll) (3) 32.75 gb/s ? ? ui j t_sj16.375 sinusoidal jitter (qpll) (3) 16.375 gb/s ? ? ui j t_sj12.5 sinusoidal jitter (qpll) (3) 12.5 gb/s ? ? ui j t_sj11.3 sinusoidal jitter (qpll) (3) 11.3 gb/s ? ? ui j t_sj10.32_qpll sinusoidal jitter (qpll) (3) 10.32 gb/s ? ? ui j t_sj10.32_cpll sinusoidal jitter (cpll) (3) 10.32 gb/s ? ? ui j t_sj9.8 sinusoidal jitter (qpll) (3) 9.8 gb/s ? ? ui j t_sj8.0_qpll sinusoidal jitter (qpll) (3) 8.0 gb/s ? ? ui j t_sj8.0_cpll sinusoidal jitter (cpll) (3) 8.0 gb/s ? ? ui j t_sj6.6_cpll sinusoidal jitter (cpll) (3) 6.6 gb/s ? ? ui j t_sj5.0 sinusoidal jitter (cpll) (3) 5.0 gb/s ? ? ui j t_sj4.25 sinusoidal jitter (cpll) (3) 4.25 gb/s ? ? ui j t_sj3.75 sinusoidal jitter (cpll) (3) 3.75 gb/s ? ? ui j t_sj3.2 sinusoidal jitter (cpll) (3) 3.2 gb/s (4) ??ui j t_sj3.2l sinusoidal jitter (cpll) (3) 3.2 gb/s (5) ??ui j t_sj2.5 sinusoidal jitter (cpll) (3) 2.5 gb/s (6) ??ui j t_sj1.25 sinusoidal jitter (cpll) (3) 1.25 gb/s (7) ??ui j t_sj500 sinusoidal jitter (cpll) (3) 500 mb/s ? ? ui sj jitter tolerance with stressed eye (2) j t_tjse3.2 total jitter with stressed eye (8) 3.2 gb/s ? ? ui j t_tjse6.6 6.6 gb/s ? ? ui j t_sjse3.2 sinusoidal jitter with stressed eye (8) 3.2 gb/s ? ? ui j t_sjse6.6 6.6 gb/s ? ? ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 10 ?12 . 3. the frequency of the injected sinusoidal jitter is 80 mhz. 4. cpll frequency at 3.2 ghz and rxout_div = 2. 5. cpll frequency at 1.6 ghz and rxout_div = 1. 6. cpll frequency at 2.5 ghz and rxout_div = 2. 7. cpll frequency at 2.5 ghz and rxout_div = 4. 8. composite jitter with rx equalizer enabled. dfe disabled. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 65 gty transceiver electrical compliance the ultrascale archit ecture gty transceiver user guide ( ug578 ) contains recommended use modes that ensure compliance for the protocols listed in table 75 . the transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. table 75: gty transceiver protocol list protocol specification serial rate (gb/s) electrical compliance caui-4 ieee 802.3-2012 25.78125 compliant 28 gb/s backplane cei-25g-lr 25?28.05 compliant interlaken oif-cei-6g, oif-cei-11gsr, oif-cei-28g-mr 4.25?25.78125 compliant 100gbase-kr4 ieee 802.3bj-2014, cei-25g-lr 25.78125 compliant (1) otu4 (otl4.4) oif-cei-28g-vsr 27.952493 compliant caui-10 ieee 802.3-2012 10.3125 compliant nppi ieee 802.3-2012 10.3125 compliant 10gbase-kr ieee 802.3-2012 10.3125 compliant sfp+ sff-8431 (sr and lr) 9.95328?11.10 compliant xfp inf-8077i, revision 4.5 10.3125 compliant rxaui cei-6g-sr 6.25 compliant xaui ieee 802.3-2012 3.125 compliant 1000base-x ieee 802.3-2012 1.25 compliant otu2 itu g.8251 10.709225 compliant otu4 (otl4.10) oif-cei-11g-sr 11.180997 compliant oc-3/12/48/192 gr-253-core 0.1555?9.956 compliant pcie gen1, 2, 3 pci express base 3.0 2.5, 5.0, and 8.0 compliant sdi smpte 424m-2006 0.27?2.97 compliant hybrid memory cube (hmc) hmc-15g -sr 10, 12.5, and 15.0 compliant cpri cpri_v_6_1_2014-07-01 0.6144?12.165 compliant passive optical network (pon) 10g-epon, 1g-epon, ng-pon2, xg-pon, and 2.5g-pon 0.155?10.3125 compliant jesd204a/b oif-cei-6g, oif-cei-11g 3.125?12.5 compliant serial rapidio rapidio specification 3.1 1.25?10.3125 compliant displayport (source only) dp 1.2b cts 1.62?5.4 compliant fibre channel fc-pi-4 1.0625?14.025 compliant sata gen1, 2, 3 serial ata revision 3.0 specification 1.5, 3.0, and 6.0 compliant sas gen1, 2, 3 t10/bsr incits 519 3.0, 6.0, and 12.0 compliant sfi-5 oif-sfi5-01.0 0.625 - 12.5 compliant notes: 1. 25 db loss at nyquist without fec. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 66 gty transceiver protocol jitter characteristics for table 76 through table 81 , the ultrascale architecture gty transceiver user guide ( ug578 ) contains recommended settings for optimal usage of protocol specific characteristics. table 76: gigabit ethernet protocol characteristics (gty transceivers) description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 ? ui table 77: xaui protocol characteristics (gty transceivers) description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? ui xaui receiver high frequency jitter tolerance total receiver jitter tolerance 3125 ? ui table 78: pci express protocol characteristics (gty transceivers) (1) standard description condition line rate (mb/s) min max units pci express transmitter jitter generation pci express gen 1 total transmitter jitter 2500 ? ui pci express gen 2 total transmitter jitter 5000 ? ui pci express gen 3 (2) total transmitter jitter uncorrelated 8000 ?ps deterministic transmitter jitter uncorrelated ? ps pci express receiver high frequency jitter tolerance pci express gen 1 total receiver jitter tolerance 2500 ? ui pci express gen 2 (2) receiver inherent timing error 5000 ?ui receiver inherent deterministic timing error ? ui pci express gen 3 (2) receiver sinusoidal jitter tolerance 0.03 mhz?1.0 mhz 8000 ?ui 1.0mhz?10mhz note 3 ?ui 10 mhz?100 mhz ? ui notes: 1. tested per card electrom echanical (cem) methodology. 2. using common refclk. 3. between 1 mhz and 10 mhz the minimum sinusoidal jitter roll-off with a slope of 20 db/decade. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 67 table 79: cei-6g and cei-11g protocol char acteristics (gty transceivers) description line rate (mb/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? ui cei-6g-lr ? ui cei-6g receiver high frequency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr ? ui cei-6g-lr ? ui cei-11g transmitter jitter generation total transmitter jitter (2) 9950?11100 cei-11g-sr ? ui cei-11g-lr/mr ? ui cei-11g receiver high frequency jitter tolerance total receiver jitter tolerance (2) 9950?11100 cei-11g-sr ? ui cei-11g-mr ? ui cei-11g-lr ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. 2. tested at line rate of 9950 mb/s using 155.46875 mhz reference clock and 11100 mb/s using 173.4375 mhz reference clock. table 80: sfp+ protocol characteristics (gty transceivers) description line rate (mb/s) min max units sfp+ transmitter jitter generation total transmitter jitter 9830.40 (1) ?ui 9953.00 10312.50 10518.75 11100.00 sfp+ receiver frequency jitter tolerance total receiver jitter tolerance 9830.40 (1) ?ui 9953.00 10312.50 10518.75 11100.00 notes: 1. line rated used for cpri over sfp+ applications. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 68 table 81: cpri protocol characteristics (gty transceivers) description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter ?ui ?ui ?ui ?ui ?ui ?ui ? note 1 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance ?ui ?ui ?ui ?ui ?ui ?ui note 1 ?ui notes: 1. tested per sfp+ specification, see table 80 . s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 69 integrated interface block for interlaken more information and documentation on solutions usin g the integrated interface block for interlaken can be found at ultrascale interlaken . the ultrascale architecture and product overview ( ds890 ) lists how many blocks are in each kintex ultrascale+ fpga. table 82: maximum performance for interlaken designs symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 (1) -2 (1) -1 -2 (1) -1 f rx_serdes_clk receive serializer/ deserializer clock 440.79 440.79 195.32 195.32 161.14 mhz f tx_serdes_clk transmit serializer/ deserializer clock 440.79 440.79 195.32 195.32 161.14 mhz f drp_clk dynamic reconfiguration port clock 250.00 250.00 250.00 250.00 250.00 mhz min max min max min max min max min max f core_clk interlaken core clock 300.00 (2) 300.00 (2) 300.00 322.27 300.00 (2) 429.69 300.00 322.27 mhz 460.00 (3) 460.00 (3) 412.50 (3) mhz f lbus_clk interlaken local bus clock 300.00 349.52 300.00 349.52 300.00 322.27 300.00 349.52 300.00 322.27 mhz notes: 1. kintex ultrascale+ fpgas in the sfvb784, ffva676, and ffva1156 packages are only supported using the 12 x 12.5g interlaken configuration. see table 67 for the f gtymax description. 2. the minimum value for core_clk is 300 mhz for the 12 x 12.5g interlaken configuration. 3. the minimum value for core_clk is 412.5 mhz for the 6 x 25.78125g interlaken configuration. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 70 integrated interface block for 100g ethernet mac and pcs more information and documentation on solutions us ing the integrated 100 gb/s ethernet block can be found at ultrascale integrated 100g ethernet mac/pcs . the ultrascale architecture and product overview ( ds890 ) lists how many blocks are in each kintex ultrascale+ fpga. integrated interface block for pci express designs more information and documentation on soluti ons for pci express designs can be found at pci express . the ultrascale architecture and product overview ( ds890 ) lists how many blocks are in each kintex ultrascale+ fpga. table 83: maximum performance for 100g ethernet designs symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 (1) -1 -2 -1 f tx_clk transmit clock 390.625 390.625 322.223 322.223 322.223 mhz f rx_clk receive clock 390.625 390.625 322.223 322.223 322.223 mhz f rx_serdes_clk receive serializer/deserializer clock 390.625 390.625 322.223 322.223 322.223 mhz f drp_clk dynamic reconfiguration port clock 250.00 250.00 250.00 250.00 250.00 mhz notes: 1. the maximum clock frequency of 390.625 mhz only applies to the caui-10 interface. the maximum clock frequency for the caui-4 interface is 322.223 mhz. table 84: maximum performance for pci express designs (1)(2) symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 f pipeclk pipe clock maximum frequency. 250.00 250.00 250.00 250.00 250.00 mhz f coreclk core clock maximum frequency. 500.00 500.00 500.00 250.00 250.00 mhz f drpclk drp clock maximum frequency. 250.00 250.00 250.00 250.00 250.00 mhz f mcapclk mcap clock maximum frequency. 125.00 125.00 125.00 125.00 125.00 mhz notes: 1. pci express gen4 operation is supported for x1, x2, x4, and x8 widths. 2. pci express gen4 operation is suppo rted in -2i and -3e speed grades. s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 71 system monitor specifications table 85: system monitor specifications parameter symbol comments/conditions min typ max units v ccadc = 1.8v 3%, v refp = 1.25v, v refn = 0v, adcclk = 5.2 mhz, t j = ?40c to 100c, typical values at t j = 40c adc accuracy (1) resolution 10 ? ? bits integral nonlinearity (2) inl ? ? 1.5 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic ??1lsbs offset error offset calibration enabled ? ? 2 lsbs gain error ??0.4% sample rate ??0.2ms/s rms code noise external 1.25v reference ? ? 1 lsbs on-chip reference ? 1 ? lsbs adc accuracy at extended temperatures resolution t j = ?55c to 125c 10 ? ? bits integral nonlinearity inl t j = ?55c to 125c ? ? 1 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic t j = ?55c to 125c ??1 analog inputs (2) adc input ranges unipolar operation 0 ? 1 v bipolar operation ?0.5 ? +0.5 v unipolar common mode range (fs input) 0 ? +0.5 v bipolar common mode range (fs input) +0.5 ? +0.6 v maximum external channel input ranges adjacent channels set within these ranges should not corrupt measurements on adjacent channels ?0.1 ? v ccadc v on-chip sensor accuracy temperature sensor error (1) t j = ?40c to 100c (with external ref) ? ? 4 c t j = ?55c to 125c (with external ref) ? ? 4.5 c t j = ?40c to 100c (with internal ref) ? ? 5 c t j = ?55c to 125c (with internal ref) ? ? 6.5 c s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 72 supply sensor error (3) supply voltages 0.72v to 1.2v, t j = ?40c to 100c (with external ref) ??0.5% supply voltages 0.72v to 1.2v, t j = ?55c to 125c (with external ref) ??1.0% all other supply voltages, t j = ?40c to 100c (with external ref) ??1.0% all other supply voltages, t j = ?55c to 125c (with external ref) ??2.0% supply voltages 0.72v to 1.2v, t j = ?40c to 100c (with internal ref) ??1.0% supply voltages 0.72v to 1.2v, t j = ?55c to 125c (with internal ref) ??2.0% all other supply voltages, t j = ?40c to 100c (with internal ref) ??1.5% all other supply voltages, t j = ?55c to 125c (with internal ref) ??2.5% conversion rate (4) conversion time?continuous t conv number of adcclk cycles 26 ? 32 cycles conversion time?event t conv number of adcclk cycles ? ? 21 cycles drp clock frequency dclk drp clock frequency 8 ? 250 mhz adc clock frequency adcclk derived from dclk 1 ? 5.2 mhz dclk duty cycle 40 ? 60 % sysmon reference (5) external reference v refp externally supplied reference voltage 1.20 1.25 1.30 v on-chip reference ground v refp pin to agnd, t j = ?40c to 100c 1.2375 1.25 1.2625 v ground v refp pin to agnd, t j = ?55c to 125c 1.225 1.25 1.275 v notes: 1. adc offset errors are removed by enabling the adc automatic offset calibration feature. the values are specified for when this feature is enabled. 2. see the analog input section in the ultrascale architecture system monitor user guide ( ug580 ). 3. supply sensor offset and gain errors ar e removed by enabling the automatic offset and gain calibration feature. the values are specified for when th is feature is enabled. 4. see the adjusting the acquisition settling time section in the ultrascale architecture sy stem monitor user guide ( ug580 ). 5. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result in a deviation from the ideal transfer function. this also impacts the accuracy of th e internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applicat ions allowing reference to vary by 4% is permitted. table 85: system monitor specifications (cont?d) parameter symbol comments/conditions min typ max units s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 73 sysmon i2c/pmbus interfaces table 86: sysmon i2c fast mode interf ace switching characteristics (1) symbol description min max units t smfckl scl low time 1.3 ? s t smfckh scl high time 0.6 ? s t smfcko sdao clock-to-out delay ? 900 ns t smfdck sdai setup time 100 ? ns f smfclk scl clock frequency ? 400 khz notes: 1. the test conditions are configured to the lvcmos 1.8v i/o standard. x-ref target - figure 9 figure 9: sysmon i2c fast mode interface timing diagram table 87: sysmon i2c standard mode inte rface switching characteristics (1) symbol description min max units t smsckl scl low time 4.7 ? s t smsckh scl high time 4.0 ? s t smscko sdao clock-to-out delay ? 3450 ns t smsdck sdai setup time 250 ? ns f smsclk scl clock frequency ? 100 khz notes: 1. the test conditions are configured to the lvcmos 1.8v i/o standard. x-ref target - figure 10 figure 10: sysmon i2c standard mode interface timing diagram t smfcko t smfdck ds922 _i2cf_042116 scl sdai sdao t smscko t smsdck ds922 _i2cs_042116 scl sdai sdao s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 74 configuration switching characteristics table 88: configuration switching characteristics symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 power-up timing characteristics t pl program latency. 7.5 7.5 7.5 7.5 7.5 ms, max t por power-on reset (40 ms ramp rate time). 57 57 57 57 57 ms, max 00000ms, min power-on reset with por override (2 ms ramp rate time). 15 15 15 15 15 ms, max 55555ms, min t program program pulse width. 250 250 250 250 250 ns, min cclk output (master mode) t icck master cclk output delay from init_b. 150 150 150 150 150 ns, min t mcckl (1) master cclk clock low time duty cycle. 40/60 40/60 40/60 40/60 40/60 %, min/max t mcckh master cclk clock high time duty cycle. 40/60 40/60 40/60 40/60 40/60 %, min/max f mcck master cclk frequency. 150 150 150 150 150 mhz, max f mcck_start master cclk frequency at start of configuration. 3.00 3.00 3.00 3.00 3.00 mhz, typ f mccktol frequency tolerance, master mode with respect to nominal cclk. 15 15 15 15 15 %, max emcclk input (master mode) t emcckl external master cclk low time. 2.5 2.5 2.5 2.5 2.5 ns, min t emcckh external master cclk high time. 2.5 2.5 2.5 2.5 2.5 ns, min f emcck external master cclk frequency. 150 150 150 150 150 mhz, max internal configuration access port f icapck internal configuration access port (icape3). 200 200 200 175 175 mhz, max slave serial mode programming switching t dcck /t cckd d in setup/hold. 3.0/0 3.0/0 3.0/0 3.5/0 3.5/0 ns, min t cco d out clock to out. 88888ns, max selectmap mode programming switching t smdcck /t smcckd d[31:00] setup/hold. 3.5/0 3.5/0 3.5/0 4.0/0 4.0/0 ns, min t smcscck /t smcckcs csi_b setup/hold. 4.0/0 4.0/0 4.0/0 4.5/0 4.5/0 ns, min t smwcck /t smcckw rdwr_b setup/hold. 10.0/0 10.0/0 10.0/0 10.0/0 10.0/0 ns, min t smckcso cso_b clock to out (330 pull-up resistor required). 77777ns, max t smco d[31:00] clock to out in readback. 88888ns, max f rbcck readback frequency. 125 125 125 125 125 mhz, max s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 75 boundary-scan port timing specifications t taptck /t tcktap tms and tdi setup/hold. 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 ns, min t tcktdo tck falling edge to tdo output. 77777ns, max f tck tck frequency. 66 66 66 66 66 mhz, max bpi master flash mode programming switching t bpicco a[28:00], rs[1:0], fcs_b, foe_b, fwe_b, adv_b clock to out. 10 10 10 10 10 ns, max t bpidcc /t bpiccd d[15:00] setup/hold. 3.5/0 3.5/0 3.5/0 4.0/0 4.0/0 ns, min spi master flash mode programming switching t spidcc /t spiccd d[03:00] setup/hold. 3.0/0 3.0/0 3.0/0 3.5/0 3.5/0 ns, min t spidcc /t spiccd d[07:04] setup/hold. 3.5/0 3.5/0 3.5/0 4.0/0 4.0/0 ns, min t spiccm mosi clock to out. 8.0 8.0 8.0 8.0 8.0 ns, max t spiccfc fcs_b clock to out. 8.0 8.0 8.0 8.0 8.0 ns, max dna port switching f dnack dna port frequency. 200 200 200 175 175 mhz, max startupe3 ports t usrcclko startupe3 usrcclko input port to cclk pin output delay. 1.00/ 6.00 1.00/ 6.70 1.00/ 7.50 1.00/ 7.50 1.00/ 7.50 ns, min/max t do do[3:0] ports to d03-d00 pins output delay. 1.00/ 6.70 1.00/ 7.70 1.00/ 8.40 1.00/ 8.40 1.00/ 8.40 ns, min/max t dts dts[3:0] ports to d03-d00 pins 3-state delays. 1.00/ 7.30 1.00/ 8.30 1.00/ 9.00 1.00/ 9.00 1.00/ 9.00 ns, min/max t fcsbo fcsbo port to fcs_b pin output delay. 1.00/ 6.90 1.00/ 8.00 1.00/ 8.60 1.00/ 8.60 1.00/ 8.60 ns, min/max t fcsbts fcsbts port to fcs_b pin 3-state delay. 1.00/ 6.90 1.00/ 8.00 1.00/ 8.60 1.00/ 8.60 1.00/ 8.60 ns, min/max t usrdoneo usrdoneo port to done pin output delay. 1.00/ 8.50 1.00/ 9.60 1.00/ 10.40 1.00/ 10.40 1.00/ 10.40 ns, min/max t usrdonets usrdonets port to done pin 3-state delay. 1.00/ 8.50 1.00/ 9.60 1.00/ 10.40 1.00/ 10.40 1.00/ 10.40 ns, min/max t di d03-d00 pins to di[3:0] ports input delay. 0.5/ 2.6 0.5/ 3.1 0.5/ 3.5 0.5/ 3.5 0.5/ 3.5 ns, min/max f cfgmclk startupe3 cfgmclk output frequency. 50 50 50 50 50 mhz, typ f cfgmclktol startupe3 cfgmclk output frequency tolerance. 15 15 15 15 15 %, max t dci_match specifies a stall in the startup cycle until the digitally controlled impedance (dci) match signals are asserted. 44444ms, max notes: 1. when the cclk is sourced from the emcclk pin with a di vide-by-one setting, the extern al emcclk must meet this duty-cycle requirement. table 88: configuration switching characteristics (cont?d) symbol description speed grade and v ccint operating voltages units 0.90v 0.85v 0.72v -3 -2 -1 -2 -1 s e n d f e e d b a c k
kintex ultrascale+ fpgas data sheet: dc and ac switching characteristics ds922 (v1.1) may 9, 2016 www.xilinx.com advance product specification 76 efuse programming conditions revision history the following table shows the revision history for this document. table 89: efuse programming conditions (1) symbol description min typ max units i plfs v ccaux supply current. ? ? 115 ma t j temperature range. ?40 ? 125 c notes: 1. do not program efuse during device conf iguration (e.g., during configuration, during configuration readback, or when readback crc is active). date version description of revisions 05/09/2016 1.1 in table 1 revised v in for hp i/o banks. updated note 5 in table 3 . added values to table 7 . added mipi_dphy_dci to table 9 , table 10 , and table 12 . updated and added notes in table 18 and table 19 . updated table 20 speed specifications for vivado design suite 2016.1. removed table 23, video codec unit performance . updated table 24 . expanded and updated table 26 . updated table 27 and table 28 . updated table 30 and table 31 with mipi d-phy values. updated the tables in the i/o standard adjustment measurement methodology section. in table 32 , added the block ram and fifo clock-to-out delays section. updated table 39 to table 43 . revised the symbol names in table 42 . revised typical values in table 47 . updated the -2 (0.72v) and -1 (0.72v) values in table 49 . added table 52 and table 70 . added note 2 to table 64 . revised table 72 . revised data and added notes to table 67 , table 82 , and table 83 . revised inl in table 85 . added notes to table 86 and table 87 . many revised sections in table 88 . 11/24/2015 1.0 initial xilinx release. s e n d f e e d b a c k
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